參數(shù)資料
型號(hào)： CAT28F102NA-12T
元件分類： PROM
英文描述： 64K X 16 FLASH 12V PROM, 120 ns, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 12/15頁(yè)
文件大?。?/td> 107K
代理商： CAT28F102NA-12T
CAT28F102
6
Doc. No. 1014, Rev. A
A.C. CHARACTERISTICS, Program/Erase Operation
VCC = +5V ±10%, unless otherwise specified.
JEDEC
Standard
28F102-10
28F102-12
Symbol
Parameter
Min. Max.
Min.
Max.
Unit
tAVAV
tWC
Write Cycle Time
100
120
ns
tAVWL
tAS
Address Setup Time
0
ns
tWLAX
tAH
Address Hold Time
40
ns
tDVWH
tDS
Data Setup Time
40
ns
tWHDX
tDH
Data Hold Time
10
ns
tELWL
tCS
CE Setup Time
0
ns
tWHEH
tCH
CE Hold Time
0
ns
tWLWH
tWP
WE Pulse Width
40
ns
tWHWL
tWPH
WE High Pulse Width
20
ns
tWHWH1(2)
-
Program Pulse Width
10
s
tWHWH2(2)
-
Erase Pulse Width
9.5
ms
tWHGL
-
Write Recovery Time
6
s
Before Read
tGHWL
-
Read Recovery Time
0
s
Before Write
tVPEL
-
VPP Setup Time to
CE
100
ns
28F102-10
Parameter
Min.
Typ. Max. Min.
Typ. Max. Unit
Chip Erase Time (3)(5)
0.5
10
0.5
10
sec
Chip Program Time(3)(4)
1
6.5
1
6.5
sec
Note:
(1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is
switched, VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25
°C, 12.0V VPP.
(4) Minimum byte programming time (excluding system overhead) is 16
s (10 s program + 6 s write recovery), while maximum is 400 s/
byte (16
s x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Erase and Programming Performance (1)
Main Menu
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