參數(shù)資料
型號(hào): CAT28F010T-90
廠商: ON SEMICONDUCTOR
元件分類: PROM
英文描述: 128K X 8 FLASH 12V PROM, 90 ns, PDSO32
封裝: 8 X 20 MM, TSOP-32
文件頁(yè)數(shù): 5/15頁(yè)
文件大?。?/td> 137K
代理商: CAT28F010T-90
CAT28F010
13
Doc. No. MD-1019, Rev. F
2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
28F010 F10
ADDRESSES
WE (E)
OE (G)
CE (W)
DATA (I/O)
VCC
VPP
tWC
tRC
tAVEL
tELAX
tWLEL
tEHQZ
tDF
tGHEL
tEHEL
tEHEH
tEHGL
tELEH
HIGH-Z
DATA IN
= 40H
DATA IN
= C0H
VALID
DATA OUT
tEHDX
tOLZ
tOE
tOH
tLZ
tCE
tVPEL
VPPH
VPPL
0V
5.0V
VCC POWER-UP
& STANDBY
SETUP PROGRAM
COMMAND
LATCH ADDRESS
& DATA
PROGRAMMING
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
VCC POWER-DOWN/
STANDBY
tWLEL
tEHWH
tELEH
tDVEH
tEHDX
(W)
(E)
Program-Verify Mode
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Program-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Abort/Reset
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.
POWER UP/DOWN PROTECTION
The CAT28F010 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F010 is reset to the Read Mode on
power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1
F ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Figure 8. Alternate A.C. Timing for Program Operation
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