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參數(shù)資料
| 型號： | CA16B2Fnn |
| 英文描述： | CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer |
| 中文描述： | CA16型2.5 Gb /秒的DWDM轉(zhuǎn)發(fā)器，16通道155 Mbits /秒復用器/解復用器 |
| 文件頁數(shù)： | 22/30頁 |
| 文件大?。?/td> | 464K |
| 代理商： | CA16B2FNN |
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22
Agere Systems Inc.
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Advance Data Sheet
March 2001
Timing Characteristics
(continued)
PC
LK
-to-PIC
LK
Timing
After powerup or RESET, the LOCKDET signal will go
active, signifying that the PLL has locked to the clock
provided on the T
X
R
EF
C
LK
input. The FIFO is initialized
on the third PIC
LK
after LOCKDET goes active. The
PC
LK
-to-PIC
LK
delay (t
D
) can have any value before the
FIFO is initialized. The t
D
is fixed at the third PICLK
after LOCKDET goes active. Once the FIFO is initial-
ized, PC
LK
and PIC
LK
cannot drift more than 5.2 ns;
tCH cannot be more than 5.2 ns.
Figure 8. PC
LK
-to-PIC
LK
Timing
PCLK
PICLK
LOCKDET
ACTIVE
3RD
IS INITALIZED AT THE THIRD RISING EDGE OF
PICLK AFTER LOCKDET GOES ACTIVE.
PCLK-TO-PICLK DELAY IS FIXED AND FIFO
2ND
1ST
tCH
tCH
tD
tD
1-1123(F)
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