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參數(shù)資料
| 型號： | CA16B2Fnn |
| 英文描述： | CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer |
| 中文描述： | CA16型2.5 Gb /秒的DWDM轉(zhuǎn)發(fā)器，16通道155 Mbits /秒復用器/解復用器 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大?。?/td> | 464K |
| 代理商： | CA16B2FNN |
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21
Agere Systems Inc.
Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Timing Characteristics
(continued)
Forward Clocking
In some applications, it is necessary to forward-clock
the data in a SONET/SDH system. In this application,
the reference clock from which the high-speed serial
clock is synthesized and the parallel data clock both
originate from the same source on the customer appli-
cation circuit. The timing control logic in the CA16 tran-
sponder transmitter automatically generates an internal
load signal that has a fixed relationship to the reference
clock. The logic takes into account the variation of the
reference clock to the internal load signal over temper-
ature and voltage. The connections required to imple-
ment this clocking method are shown in Figure 7. The
setup and hold times for PIC
LK
to TxD[0:15] must be
met by the customer logic.
Possible problems: to meet the jitter generation specifi-
cations required by SONET/SDH, the jitter of the refer-
ence clock must be minimized. It could be difficult to
meet the SONET jitter generation specifications using
a reference clock generated from the customer logic.
Figure 7. Forward Clocking of the CA16 Transponder
CUSTOMER LOGIC
CA16 TRANSPONDER
FIFO
PLL
DIVIDER
T
X
REFCLK
16
PHERR
PHINIT
PCLK
PICLK
LOCKDET
TIMING
GENERATOR
INTERNAL
PCLK
TXD[0:15]
CLOCK
DATA
CENTERS
FIFO
OSCILLATOR
155.52 MHz
±
20 ppm
T
X
REFCLK
CLOCK
BUFFER
1-1122(F).a
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