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參數(shù)資料
| 型號(hào)： | C9853AT |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | C9853AT |
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+/+
…when timing is critical
C9853
High Performance Pentium
III Clock Generator
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
1.0
4/13/2000
MILPITAS, CA TEL 408-263-6300, FAX 408-263-6571
Page 7 of 16
http://www.imicorp.com
AC Parameters (Cont.)
133 MHz CPU
100 MHz CPU
Characteristic
Symbol
Min
Max
Min
Max
Units
Notes
3V66 CLK period
TPeriod
15.0
16.0
15.0
15.2
nS
3V66 CLK high time
THIGH
5.25
N/A
5.25
N/A
nS
2, 9
3V66 CLK low time
TLOW
5.05
N/A
5.05
N/A
nS
5, 10
3V66 CLK rise time
TRISE
0.5
2.0
0.5
2.0
nS
6, 10
3V66 CLK fall time
TFALL
0.5
2.0
0.5
2.0
nS
8
3V66 Duty Cycle
Tdc
45
55
45
55
%
11
3V66 to 3V66 clock skew
Tskew
250
pS
3V66 Cycle to Cycle jitter
TJcc
300 pS
pS
12
PCI CLK period
TPeriod
30.0
nS
8
PCI CLK high time
THIGH
12.0
nS
2, 9
PCI CLK low time
TLOW
12.0
nS
5, 10
PCI CLK rise time
TRISE
0.5
2.0
0.5
2.0
nS
6, 10
PCI CLK fall time
TFALL
0.5
2.0
0.5
2.0
nS
8
PCI Duty Cycle
Tdc
45
55
45
55
%
11
PCI to PCI clock skew
Tskew
500
pS
PCI Cycle to Cycle jitter
TJcc
500
pS
12
Output enable delay (all outputs)
tpZL, tpZH
1.0
10.0
1.0
10.0
nS
Output disable delay (all outputs)
tpLZ, tpZH
1.0
10.0
1.0
10.0
nS
All clock Stabilization from power-up
Tstable
3
nS
7
Notes:
1.
All output drivers have monotonic rise/fall times through the specified VOL/VOH levels.
2.
Period, jitter, offset and skew measured on rising edge @ 1.25V for 2.5V clocks and @1.5V for 3.3V clocks.
3.
The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the host clock divided by three at
Host = 100 MHz.
4.
3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided
by three for Host = 100 MHz.
5.
THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
6.
TLOW is measured at 0.4V for all outputs.
7.
The time specified is measured from when VDD achieves its nominal operating level (typical condition VDD = 3.3V)
till the frequency output is stable and operating within specification.
8.
TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA)
JEDEC Specification.
9.
The average period over any 1 uS period of time is greater than the minimum specified period.
10. Calculated at minimum edge-rate (1V/nS) to guarantee 45/55% duty-cycle. Pulsewidth is wider at faster edge-rate
ensuring duty-cycle specification is met.
11. CPU clock test load is Rs=33.2 Ohms, Rp = 49.9.
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