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參數(shù)資料
| 型號： | C9853AT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 145K |
| 代理商： | C9853AT |
+/+
…when timing is critical
C9853
High Performance Pentium
III Clock Generator
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
1.0
4/13/2000
MILPITAS, CA TEL 408-263-6300, FAX 408-263-6571
Page 6 of 16
http://www.imicorp.com
AC Parameters
133 MHz CPU
100 MHz CPU
Characteristic
Symbol
Min
Max
Min
Max
Units
Notes
CPU CLK period - average
TPeriod
7.5
7.65
10.0
10.2
nS
11
Absolute minimum CPU CLK Period
Abs/MinPeriod
7.35
N/A
9.85
N/A
nS
11
Output Current (CPU)
Ioh
12.9
14.9
12/9
14.9
mA
11
(Voltage at given load)
(Voh)
(0.66)
(0.76)
(0.66)
(0.75)
(V)
Vol
VSS=
0.0
0.05
VSS =
0.0
0.05
V
11
Vcrossover
45%
Voh
55%
Voh
45%
Voh
55%
Voh
V11
Host/CPU CLK rise time
TRISE
175
700
175
700
pS
11, 12
Host/CPU CLK fall time
TFALL
175
700
175
700
pS
11, 12
Rise time and fall time matching
Rise/Fall
Matching
20%
11
Overshoot
Voh +
0.2V
Voh +
0.2V
11
Undershoot
-0.2
V
11
Cycle to Cycle jitter
TJcc
200 pS
pS
13
CPU to CPU clock skew
Tskew
150
pS
Duty Cycle
Tdc
45
55
45
55
%
11
Mref, Mref_b CLK period
TPeriod
15.0
15.3
20.
20.4
nS
2, 9
Mref, Mref_b CLK high time
THIGH
5.25
N/A
7.5
N/A
nS
5, 10
Mref, Mref_b CLK low time
TLOW
5.05
N/A
7.3
N/A
nS
6, 10
Mref, Mref_b CLK rise time
TRISE
0.4
1.6
0.4
1.6
nS
8
Mref, Mref_b, CLK fall time
TFALL
0.4
1.6
0.4
1.6
nS
8
Mref and Mref_b Duty Cycle
Tdc
45
55
45
55
%
11
Mref & Mref_b Cycle to Cycle jitter
TJcc
250 pS
pS
12
REF CLK rise time
TRISE
2.0
nS
8
REF CLK fall time
TFALL
2.0
nS
8
REF Duty Cycle
Tdc
45
55
45
55
%
11
REF Cycle to Cycle jitter
TJcc
1.0
nS
12
48M CLK rise time
TRISE
2.0
nS
8
48M CLK fall time
TFALL
2.0
nS
8
48M Duty Cycle
Tdc
45
55
45
55
%
11
48M Cycle to Cycle jitter
TJcc
350
pS
12
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