參數(shù)資料
型號(hào)： C9853AT
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： TSSOP-48
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 145K
代理商： C9853AT
+/+
…when timing is critical
C9853
High Performance Pentium
III Clock Generator
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
1.0
4/13/2000
MILPITAS, CA TEL 408-263-6300, FAX 408-263-6571
Page 4 of 16
http://www.imicorp.com
Power on Bi-Directional Pins
Power Up Condition:
Pins 1, 23, 24, and 48 are Power up bi-directional pins and are used for different features in this device (see Pin
description, Page 2). During power-up, these pins are in input mode (see Fig 2, below), therefore, they are considered
input select pins internal to the IC. After a settling time, the Selection data is latch into internal control registers and
these pins become toggling clock outputs.
-
Hi-Z Inputs
Toggle Outputs
Power Supply
Ramp
Select Data is latched into register then pin becomes clock output signal.
VDD Rail
Ref1/MultSel0
Ref2/MultSel1
48M0/SelA
48M1/SelB
Strapping Resistor Options for pins with internal
Pull-ups:
The power up bidirectional pins have a large value pull-
up each (250K
), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
3mS settling time), then it is recommended to use an
external Pullup (Rup) in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see Fig. 2A and Fig. 2B.
Fig. 2A represents an additional pull up resistor 50K
connected from the pin to the power line, which allows
a faster pull to a high level.If a selection “0” is desired,
then a jumper is placed on JP1 to a 5K
resistor as
implemented as shown in Fig.2A. Please note the
selection resistors (Rup, and Rdn
) are placed before
the Damping resistor (Rd) close to the pin.
Fig. 2B represent a single resistor 10K
connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads
1 and 2.
Load
Fig.2A
Fig.2B
Vdd
Rup
50K
Rd
IMI C9853
Bidirectional
JP1
JUMPER
JP2
3 Way Jumper
Rsel
10K
Rd
IMI C9853
Bidirectional
Rdn
5K
Fig. 1
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