參數(shù)資料
型號(hào)： BXM80526B500256
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 500 MHz, MICROPROCESSOR, CPGA495
封裝： MICRO PGA-495
文件頁(yè)數(shù)： 69/84頁(yè)
文件大?。?/td> 450K
代理商： BXM80526B500256
Mobile Pentium III Processor in BGA2 and Micro-PGA2 Packages Datasheet
Intel Corporation
63
DRDY# (I/O - GTL+)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating
valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle
clocks. This signal must be connected to the appropriate pins/balls on both agents on the system
bus.
EDGCTRLP (Analog)
The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the GTL+ output
buffers. Connect the signal to VSS with a 110-, 1% resistor.
FERR# (O - 1.5V Tolerant Open-drain)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked
floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it
is included for compatibility with systems using DOS-type floating-point error reporting.
FLUSH# (I - 1.5V Tolerant)
When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache
lines in the Modified state and invalidates all internal cache lines. At the completion of a flush
operation, the processor issues a Flush Acknowledge transaction. The processor stops caching any
new data while the FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to
determine its power-on configuration.
GHI# (I - 1.5V Tolerant)
The GHI# signal controls which operating mode bus ratio is selected in a mobile Pentium III
processor featuring Intel SpeedStep technology. On the processor featuring Intel SpeedStep
technology, this signal is latched when BCLK restarts in Deep Sleep state and determines which
of two bus ratios is selected for operation. This signal is ignored when the processor is not in the
Deep Sleep state. This signal is a “Don’t Care” on processors that do not feature Intel SpeedStep
technology. This signal has an on-die pull-up to VCCT and should be driven with an Open-drain
driver with no external pull-up.
HIT# (I/O - GTL+), HITM# (I/O - GTL+)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation
results, and must be connected to the appropriate pins/balls on both agents on the system bus.
Either bus agent can assert both HIT# and HITM# together to indicate that it requires a snoop
stall, which can be continued by reasserting HIT# and HITM# together.
IERR# (O - 1.5V Tolerant Open-drain)
The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus.
相關(guān)PDF資料
PDF描述
BXM80526B600256 64-BIT, 600 MHz, MICROPROCESSOR, CPGA495
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BY8408 Fast high-voltage soft-recovery rectifiers
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