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| 型號(hào)： | BX80532KC2600D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2600 MHz, MICROPROCESSOR |
| 文件頁(yè)數(shù)： | 121/129頁(yè) |
| 文件大小： | 1640K |
| 代理商： | BX80532KC2600D |
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Intel Xeon Processor with 512 KB L2 Cache
Datasheet
91
SM_CLK
I/O
The SM_CLK (SMBus Clock) signal is an input clock to the system management
logic which is required for operation of the system management features of the
processor. This clock is driven by the SMBus controller and is asynchronous to
other clocks in the processor. The processor includes a 10 K
pull-up resistor to
SM_VCC for this signal.
SM_DAT
I/O
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus
devices.The processor includes a 10 K
pull-up resistor to SM_V
CC for this signal.
SM_EP_A[2:0]
I
The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in
conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors. To set an SM_EP_A line high, a
pull-up resistor should be used that is no larger than 1 K
. The processor includes
a 10 K
pull-down resistor to V
SS for each of these signals. For more information
on the usage of these pins, see Section 7.4.8.
SM_TS_A[1:0]
I
The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus
in conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors.
The device’s addressing, as implemented, includes a Hi-Z state for both address
pins. The use of the Hi-Z state is achieved by leaving the input floating
(unconnected). For more information on the usage of these pins, see Section 7.4.8.
SM_VCC
I
Provides power to the SMBus components on the processor, as well as to the
processor VID logic. The baseboard MUST provide SM_Vcc to the processor. See
Figure 19 “Example 3.3 VDC/SM_VCC Sequencing” on page 44 for further details.
SM_WP
I
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to SM_VCC.The
processor includes a 10 K
pull-down resistor to V
SS for this signal.
SMI#
I
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, processors save the current state
and enter System Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs.
3
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the front
side bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
3
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
Table 41. Signal Definitions (Page 8 of 10)
Name
Type
Description
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61582D0-290Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-100K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-100Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-291W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61582D1-391Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80532KC2600DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.6GHZ - Boxed Product (Development Kits) |
| BX80532KC2800DU | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80532KC2800F | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 2.8GHZ - Boxed Product (Development Kits) |
| BX80532KC3000D | 制造商:Intel 功能描述:MPU XEON PROCESSOR NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
| BX80532KC3000H | 制造商:Intel 功能描述:MPU XEON NETBURST 64-BIT 0.13UM 3GHZ - Boxed Product (Development Kits) |
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