參數(shù)資料
型號: BUK100-50DL
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: PowerMOS transistor Logic level TOPFET(功率MOS晶體管邏輯電平TOPFET)
中文描述: 13.5 A, 50 V, 0.125 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB
封裝: PLASTIC, TO-220AB, 3 PIN
文件頁數(shù): 4/10頁
文件大?。?/td> 84K
代理商: BUK100-50DL
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
BUK100-50DL
INPUT CHARACTERISTICS
T
mb
= 25 C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IS(TO)
I
IS
Input threshold voltage
Input supply current
V
DS
= 5 V; I
D
= 1 mA
normal operation;
1.0
100
-
2.0
1.0
1.5
200
160
2.6
-
2.0
350
270
3.5
-
V
μ
A
μ
A
V
V
IS
= 5 V
V
IS
= 4 V
T
j
= 25 C
T
j
= 150 C
V
IS
= 5 V
V
IS
= 3.5 V
V
ISR
Protection reset voltage
1
I
ISL
Input supply current
protection latched;
-
-
6
-
-
330
240
-
33
50
650
430
-
-
-
μ
A
μ
A
V
k
k
V
(BR)IS
R
IG
Input breakdown voltage
Input series resistance
to gate of power MOSFET
I
I
= 10 mA
T
j
= 25 C
T
j
= 150 C
SWITCHING CHARACTERISTICS
T
mb
= 25 C. R
I
= 50
. Refer to waveform figure and test circuit.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
t
d on
t
r
t
d off
t
f
Turn-on delay time
V
DD
= 13 V; V
IS
= 5 V
resistive load R
L
= 4
V
DD
= 13 V; V
IS
= 0 V
resistive load R
L
= 4
-
8
-
μ
s
μ
s
μ
s
μ
s
Rise time
-
40
-
Turn-off delay time
-
40
-
Fall time
-
35
-
REVERSE DIODE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
I
S
Continuous forward current
T
mb
25 C; V
IS
= 0 V
-
15
A
REVERSE DIODE CHARACTERISTICS
T
mb
= 25 C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
SDO
t
rr
Forward voltage
I
S
= 15 A; V
IS
= 0 V; t
p
= 300
μ
s
not applicable
2
-
1.0
1.5
V
Reverse recovery time
-
-
-
-
1
The input voltage below which the overload protection circuits will be reset.
2
The reverse diode of this type is not intended for applications requiring fast reverse recovery.
November 1996
4
Rev 1.200
相關(guān)PDF資料
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BUK100-50GL PowerMOS transistor Logic level TOPFET(功率MOS晶體管邏輯電平TOPFET)
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BUK101-50GL PowerMOS transistor Logic level TOPFET(功率MOS晶體管邏輯電平TOPFET)
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