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參數(shù)資料
| 型號(hào)： | BU5071 |
| 文件頁(yè)數(shù)： | 8/30頁(yè) |
| 文件大?。?/td> | 393K |
| 代理商： | BU5071 |
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CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to
the Control Register is as shown in table 1. The
secondbyte functionsare detailed in table 2.
MASTERCLOCK FREQUENCY SELECTION
A Master clock must be provided to COMBO IIG
for operation of the filter and coding/decoding
functions. The MCLK frequency must be either
512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
4.096 MHz and must be synchronous with BCLK.
Bits F1 and F0 (see table 2) must be set during
initializationto select the correct internal divider.
CODING LAW SELECTION
Bits ”MA” and ”IA” in table 2 permit the selection
of
μ
255 coding or A-law coding with or without
even-bitinversion.
ANALOGLOOPBACK
Analog Loopback mode is entered by setting the
”AL” and ”DL” bitsin the ControlRegister as shown
intable 2. In the analogloopbackmode, the Trans-
mit input VF
X
I is isolated from the input pin and in-
ternally connected to the VF
R
O output, forming a
loop from the Receive PCM Register back to the
Transmit PCM Register. The VF
R
O pinremainsac-
tive, and the programmed settings of the Transmit
and Receive gains remain unchanged, thus care
must be taken to ensure that overload levels are
notexceededanywherein the loop.
Hybrid balancing must be disabled for meaning
fulanalog loopback Function.
DIGITALLOOPBACK
Digital Loopback mode is entered by setting the
”DL” bitinthe Control Registeras shown intable 2.
Bit Number
Function
7
6
5
4
3
2
1
0
F1
F0
MA
IA
DN
DL
AL
PP
0
0
1
1
0
1
0
1
MCLK = 512 kHz
MCLK = 1. 536 or 1. 544 MHz
MCLK = 2. 048 MHz
*
MCLK = 4. 096 MHz
Select
μ
. 255 Law
*
A–law, Including Even Bit Inversion
A–Law, No Even Bit Inversion
0
1
1
X
0
1
0
1
Delayed Data Timing
Non–delayed Data Timing
*
Normal Operation
*
Digital Loopback
Analog Loopback
0
1
0
0
X
1
0
1
Power Amp Enabled in PDN
Power Amp Disabled in PDN
*
Table 2:
Control RegisterByte 2 Functions
Table 3:
Coding Law Conventions.
m255 Law
MSB LSB
0
1
1
0
True A-law with
even bit inversion
MSB LSB
1
0
0
0
1
1
0
A-law without
even bit inversion
MSB LSB
1
1
0
0
0
1
1
V
IN
= +Full Scale
V
IN
= 0V
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
V
IN
= -Full Scale
Note:
The MSB isalways the first PCM bit shifted in or out of COMBO IIG.
(*) State at power-on initialization (bit 4 = 0)
TS5070- TS5071
8/30
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