- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369553 > BU5071 PDF資料下載
參數(shù)資料
| 型號： | BU5071 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 393K |
| 代理商： | BU5071 |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
struction;andbit 0 is notused.To shiftcontrol data
into COMBO IIG, CCLK must be pulsed high 8
timeswhileCS is low. Data on theCI or CI/Oinput
is shifted into the serial input register on the falling
edge of each CCLK pulse. After all data is shifted
in, the contents of the input shift register are de-
coded, and may indicate that a 2nd byte of control
datawill follow.Thissecond byte may eitherbe de-
finedbyasecondbyte-wideCSpulseormayfollow
the first continuously,i.e.it is not mandatoryfor CS
to returnhigh in betweenthe first and second con-
trol bytes.Onthe fallingedgeof the 8
th
CCLK clock
pulse inthe 2nd controlbyte the datais loadedinto
theappropriateprogrammableregister.CSmayre-
mainlow continuouslywhen programming succes-
Table 1:
ProgrammableRegister Instructions
siveregisters,ifdesired.HoweverCSshouldbeset
high when no datatransfers are in progress.
ToreadbackinterfaceLatchdataor statusinforma-
tionfrom COMBO IIG,thefirst byteof theappropri-
ateinstructionisstrobedinduringthefirstCSpulse,
asdefinedintable1.CSmust thenbe takenlow for
a further 8 CCLK cycles, during which the data is
shifted ontothe CO or CI/O pin on therising edges
of CCLK. When CS is high the CO or CI/O pinis in
thehigh-impedanceTRI-STATE, enablingthe CI/O
pins of many devices to be multiplexed together.
Thus,to summarize, 2-byte READ and WRITE in-
structions may use eithertwo 8-bitwideCS pulses
or a single16-bit wide CS pulse.
Function
Byte 1
Byte 2
7
6
5
4
3
2
1
0
Single Byte Power–up/down
P
X
X
X
X
X
0
X
None
Write Control Register
Read–back Control Register
P
P
0
0
0
0
0
0
0
0
0
1
1
1
X
X
See Table 2
See Table 2
Write Latch Direction Register (LDR)
Read Latch DirectionRegister
P
P
0
0
0
0
1
1
0
0
0
1
1
1
X
X
See Table 4
See Table 4
Write Latch Content Register (ILR)
Read Latch Content Register
P
P
0
0
0
0
0
0
1
1
0
1
1
1
X
X
See Table 5
See Table 5
Write Transmit Time–slot/port
Read–back Transmit Time–slot/port
P
P
1
1
0
0
1
1
0
0
0
1
1
1
X
X
See Table 6
See Table 6
Write Receive Time–slot/port
Read–back Receive Time–slot/port
P
P
1
1
0
0
0
0
1
1
0
1
1
1
X
X
See Table 6
See Table 6
Write Transmit Gain Register
Read Transmit Gain Register
P
P
0
0
1
1
0
0
1
1
0
1
1
1
X
X
See Table 7
See Table 7
Write Receive Gain Register
Read Receive Gain Register
P
P
0
0
1
1
0
0
0
0
0
1
1
1
X
X
See Table 8
See Table 8
Write Hybrid Balance Register
≠
1
Read Hybrid Balance Register
≠
1
P
P
0
0
1
1
1
1
0
0
0
1
1
1
X
X
See Table 9
See Table 9
Write Hybrid Balance Register
≠
2
Read Hybrid Balance Register
≠
2
P
P
0
0
1
1
1
1
1
1
0
1
1
1
X
X
See Table 10
See Table 10
Write Hybrid Balance Register
≠
3
Read Hybrid Balance Register
≠
3
P
P
1
1
0
0
0
0
0
0
0
1
1
1
X
X
PROGRAMMABLE FUNCTIONS
POWER-UP/DOWN CONTROL
Following power-on initialization, power-up and
power-down control may be accomplished by
writing any of the control instructions listed in ta-
ble 1 into COMBO IIG with the ”P” bit set to ”0”
for power-up or ”1” for power-down. Normally it is
recommended that all programmablefunctions be
initially programmed while the device is powered
down. Power state control can then be included
with the last programming instruction or the sepa-
rate single-byte instruction. Any of the program-
mable registers may also be modified while the
device is powered-up or down be setting the ”P”
bit as indicated. When the power up or down con-
trol is entered as a single byte instruction, bit one
(1) must be setto a 0.
When a power-up command is given, all de-acti-
vated circuits are activated, but the TRI-STATE
PCM output(s), D
X
0 (and D
X
1), will remain in the
high impedance state until the second FS
X
pulse
after power-up.
Notes:
1. Bit 7 of bytes 1 and 2 is always the first bit clocked into or out of the CI, CO or CI/CO pin.
2. ”P” is the power-up/down control bit,see ”Power-up” section (”0” = Power Up ”1” = Power Down).
TS5070 - TS5071
7/30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU508AD | TRANSISTOR | BJT | NPN | 700V V(BR)CEO | 8A I(C) | TO-218AC |
| BU508DR | TRANSISTOR | BJT | NPN | 700V V(BR)CEO | 8A I(C) | TO-218VAR |
| BU508FI | TRANSISTOR | BJT | NPN | 700V V(BR)CEO | 5A I(C) | TO-218 |
| BU508DFI | HIGH VOLTAGE FAST-SWITCHING NPN POWER TRANSISTORS |
| BU508AF | NPN POWER TRANSISTORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU507-1 | 制造商:Thomas & Betts 功能描述:2 1/2 BUSHING,RGD/IMC,NM,INSUL,EA |
| BU-5076-C-24-0 | 功能描述:測試插頭和測試插座 Black BNC Male to Bl RoHS:否 制造商:Johnson / Emerson Connectivity Solutions 設(shè)備類型:Binding Posts 類型:Threaded stud 顏色:Black 電流額定值:15 A 觸點電鍍:Silver |
| BU-5076-C-36-0 | 功能描述:測試插頭和測試插座 Black BNC Male to Bl RoHS:否 制造商:Johnson / Emerson Connectivity Solutions 設(shè)備類型:Binding Posts 類型:Threaded stud 顏色:Black 電流額定值:15 A 觸點電鍍:Silver |
| BU-5076-C-48-0 | 功能描述:測試插頭和測試插座 Black BNC Male to Bl RoHS:否 制造商:Johnson / Emerson Connectivity Solutions 設(shè)備類型:Binding Posts 類型:Threaded stud 顏色:Black 電流額定值:15 A 觸點電鍍:Silver |
| BU-5078-C-24-0 | 功能描述:測試插頭和測試插座 Black BNC Male to Go RoHS:否 制造商:Johnson / Emerson Connectivity Solutions 設(shè)備類型:Binding Posts 類型:Threaded stud 顏色:Black 電流額定值:15 A 觸點電鍍:Silver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。