參數(shù)資料
型號(hào)： BU5071
文件頁(yè)數(shù)： 4/30頁(yè)
文件大小： 393K
代理商： BU5071
TRANSMIT SECTION
Name
Pin
Type
TS5070
FN
TS5071
N
Function
Description
FS
X
I
22
15
Transmit
Frame Sync.
Normally a pulse or squarewave waveform with an 8 kHz
repetition rate is applied to this input to define the start of
the transmit time-slot assigned to this device (non-delayed
data mode) or the start of the transmit frame (delayed
data mode using the internal time-slot assignment
counter).
VF
X
I
I
28
20
Transmit
Analog
This isa high–impedance input. Voicefrequency signals
present on this input are encoded as an A–law or
μ
–law
PCM bit stream and shifted out on the selected D
X
pin.
D
X
0
D
X
1
0
0
18
19
13
–
Transmit Data
D
X
1 is availableon the TS5070 only, D
X
0 isavailable on
all devices. These transmit data TRI–STATE
outputs
remain in the high impedance state except during the
assigned transmit time–slot on the assigned port, during
which the transmit PCM data byte is shifted out onthe
rising edges of BCLK.
TS
X
0
TS
X
1
0
0
20
21
14
–
Transmit
Time–slot
TS
X
1 is availableon the TS5070 only.
TS
X
0 is availableon all devices. Normally these opendrain
outputs are floating in a high impedance state except
when a time–slot is activeon one of the D
X
outputs, when
the apppropriate TS
X
output pulls low to
enable a backplane line–driver. Should be strapped to
ground (GND) when not used.
RECEIVESECTION
Name
Pin
Type
TS5070
FN
TS5071
N
Function
Description
FS
R
I
8
6
Receive Frame
Sync.
Normally a pulse or squarewave waveform with an 8 kHz
repetition rate is applied to this input to define the start of
the receive time–slot assigned to this device (non-delayed
frame mode) or the start of the receive frame (delayed
frame mode using the internal time-slot assignment
counter.
VF
R
0
0
2
2
Receive Analog
The receive analog power amplifier output, capable of
driving load impedances as low as 300
(depending on
the peak overload level required). PCM data receivedon
the assigned D
R
pinis decoded and appears at this output
as voice frequency signals.
D
R
0
D
R
1
I
I
10
9
7
–
Receive Data
D
R
1 isavailable on the TS5070 only, D
R
0 isavailable on
all devices. These receive data input(s)are inactive
except during the assigned receive time–slot of the
assigned port when the receive PCM data is shifted in on
the falling edges of BCLK.
TS5070- TS5071
4/30
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