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參數(shù)資料
| 型號(hào)： | BU5071 |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 393K |
| 代理商： | BU5071 |
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Alternatively, the internal time-slot assignment
counters and comparators can be used to access
anytime-slotinaframe,usingtheframesyncinputs
as marker pulses for the beginningof transmit and
receive time-slot 0. In thismode,a frame maycon-
sistof up to 64 time-slots of 8 bits each. Atime-slot
isassignedbya2-byteinstructionasshownintable
1 and6. The last6 bits of thesecond byte indicate
the selected time-slot from 0-63 using straight bi-
nary notation. A new assignment becomes active
on the second frame following the end of the Chip
Selectfor the secondcontrol byte. The ”EN” bit al-
lowsthePCM inputsD
R
0/1 oroutputsD
X
0/1asap-
propriate,to be enabledor disabled.
Time-Slot Assignmentmode requires that the FS
X
andFS
R
pulsesmustconformto thedelayedtiming
format shown in figure6.
PORTSELECTION
On the TS5070 only, an additional capability is
available : 2 Transmit serial PCM ports, D
X
0 and
D
X
1, and2 receiveserialPCMports,D
R
0 andD
R
1,
are providedto enabletwo-way space switching to
be implemented. Port selections for transmit and
receive are made within the appropriate time-slot
assignmentinstructionusingthe”PS” bitinthesec-
ond byte.
On the TS5071,onlyports D
X
0 and D
R
0 are avail-
able, thereforethe ”PS” bitMUST always beset to
0 for these devices.
Table 6 shows the format for the second byte of
bothtransmitandreceive time-slotandportassign-
ment instructions.
TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB
steps by writing to the Transmit Gain Register as
defined in tables 1 and 7. This corresponds to a
range of 0 dBm0 levels at VF
X
I between 1.619
Vrms and 0.087 Vrms (equivalent to + 6.4 dBmto
– 19.0 dBm in 600
).
To calculate the binary code for byte 2 of this in-
struction for any desired input 0 dBm0 level in
Vrms, take the nearest integer to the decimal
numbergiven by :
and convert to thebinary equivalent. Some exam-
plesare givenin table7.
Bit Number
0dBm0 Test Leve at VF
X
I
In dBm (Into 600
)
7
6
5
4
3
2
1
0
In Vrms (approx.)
0
0
0
0
0
0
0
0
No Output
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
– 19
– 18.9
0.087
0.088
1
0
1
1
1
1
1
1
0
0.775
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
+6.3
+6.4
1.60
1.62
Table 7:
Byte 2 of Transmit Gain Instructions.
(*) State at power initialization
RECEIVEGAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB
stepsbywritingto theReceiveGainRegisterasde-
finedin table1 and 8. Note the following restriction
on outputdrive capability :
a) 0 dBm0 levels
≤
8.1dBm at VF
R
O may be
driven into a load of
≥
15 k
to GND,
b) 0 dBm0 levels
≤
7.6dBm at VF
R
O may be
driven into a load of
≥
600
to GND,
c) 0 dBm levels
≤
6.9dBmat VF
R
O may be driven
into a load of
≥
300
to GND.
To calculate the binary code for byte 2 of this in-
struction for any desired output 0 dBm0 level in
Vrms, take the nearestinteger to thedecimal num-
bergiven by :
200 Xlog
10
(V/
√
6
) + 174
and convert to thebinary equivalent. Some exam-
plesare givenin table8.
200 Xlog
10
(V/
√
6
) + 191
TS5070- TS5071
10/30
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| BU508DR | TRANSISTOR | BJT | NPN | 700V V(BR)CEO | 8A I(C) | TO-218VAR |
| BU508FI | TRANSISTOR | BJT | NPN | 700V V(BR)CEO | 5A I(C) | TO-218 |
| BU508DFI | HIGH VOLTAGE FAST-SWITCHING NPN POWER TRANSISTORS |
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