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參數(shù)資料
| 型號(hào)： | BU2050F-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DRVR SER/PAR I/O 8BIT SOP14 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1376 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | BU2050F-E2DKR |
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BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
15/24
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
【BD7851FP】
●Pin descriptions
Pin No.
Pin Name
Function
1
GND
Ground
2
R_Iref
Reference Current Output Current setting
3
LATCH
Latch Signal Input
4
S_IN
Serial Data Input
5～15
OUT16
～OUT6
Reference Current Output
16
P_GND
Ground for Driver
17～21
OUT5
～OUT1
Reference Current Output
22
SOUT
Serial Data Output
23
CLOCK
Clock Input
24
ENABLE
25
VCC
●Timing chart
Fig. 12
1.
After the power is turned on and the voltage is stabilized, LATCH should be activated, after clocking 16 data bits
into the S_IN terminal.
2.
OUTn parallel output data of the shift register is set after the 16
th clock by the LATCH.
3.
The final stage data of the shift register is outputted to the SOUT by synchronizing with the rise time of the
CLOCK.
4.
Since the LATCH is a label latch, data is retained in the “L” section and renewed in the “H” section of the LATCH.
5.
Data retained in the internal latch circuit is outputted when the ENABLE is in the “L” section. When the ENABLE
is in the “H” section, data is fixed in the “H” section.
CLOCK
LATCH
S_IN
DATA16
DATA15
DATA14
DATA2
DATA1
OUTn
Previous DATA
DATA
SOUT
Previous
DATA15
Previous
DATA14
Previous
DATA2
DATA16
Previous
DATA1
DATA15
DATA14
ENABLE
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