- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10662 > BU2050F-E2 (Rohm Semiconductor)IC DRVR SER/PAR I/O 8BIT SOP14 PDF資料下載
參數(shù)資料
| 型號(hào)： | BU2050F-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁(yè)數(shù)： | 18/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DRVR SER/PAR I/O 8BIT SOP14 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1376 (CN2011-ZH PDF) |
| 其它名稱： | BU2050F-E2DKR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)當(dāng)前第18頁(yè)
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
9/24
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
【BU2092F/BU2092FV】
●Pin descriptions
●Timing chart
Fig. 4
1.
After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into
the DATA terminal.
2.
Qx parallel output data of the shift register is set after the 12
th clock by the LCK.
3.
Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
4.
Data retained in the internal latch circuit is output when the OE is in the “L” section.
［Truth Table］
Input
Function
CLOCK
DATA
LCK
OE
×
H
Output (Q0～Q11) Disable
×
L
Output (Q0～Q11) Enable
L
×
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
H
×
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
×
The data of shift register has no change.
×
The data of shift register is transferred to the storage register.
×
The data of storage register has no change.
Pin No.
Pin Name
I/O
Function
1
VSS
-
GND
2
DATA
I
Serial Data Input
3
CLOCK
I
Shift clock of DATA (Rising Edge Trigger)
4
LCK
I
Latch clock of DATA (Rising Edge Trigger)
5～11,
14～18
Q0～Q11
O
Parallel Data Output (Nch Open Drain FET)
Latch Data
L
H
Output FET
ON
OFF
12, 13
N.C.
-
Non connected
17
OE
I
Output Enable (“H” level : output FET is OFF)
18
VDD
-
Power Supply
CLOCK
LCK
DATA
DATA11
DATA10
DATA9
DATA1
DATA0
OE
Qx
Previous DATA
DATA11～0
“H”
Note) Diagram shows a status where a pull-up resistor is connected to output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-J7K-MY-F3 | CONVERTER MOD DC/DC 40V 50W |
| VI-B10-IV-F1 | CONVERTER MOD DC/DC 5V 150W |
| VI-J7K-MY-F1 | CONVERTER MOD DC/DC 40V 50W |
| MAX920ESA+T | IC COMPARATOR BTR 8-SOIC |
| VI-J72-MY-F1 | CONVERTER MOD DC/DC 15V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU2050FP-E2 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Serial / Parallel 4-input Drivers |
| BU2050FS-E2 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Serial / Parallel 4-input Drivers |
| BU2050FV-E2 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Serial / Parallel 4-input Drivers |
| BU206 | 制造商:Thomas & Betts 功能描述:2" BUSHING,RGD/IMC,DC,HVY REINF RI 制造商:Thomas & Betts 功能描述:Fittings Bushing 2inch Zinc |
| BU-206+J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TESTPLATINE 3 BOARDS MIT 140 TESTKABELN |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。