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參數(shù)資料
| 型號： | BU2050F-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRVR SER/PAR I/O 8BIT SOP14 |
| 標準包裝： | 1 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 8/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1376 (CN2011-ZH PDF) |
| 其它名稱： | BU2050F-E2DKR |
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
12/24
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
【BU2099FV】
●Pin descriptions
Pin No.
Pin Name
I/O
Function
1
VSS
-
GND
2
N.C.
-
Non connected
3
DATA
I
Serial Data Input
4
CLOCK
I
Shift clock of Shift register (Rising Edge Trigger)
5
LCK
I
Latch clock of Storage register (Rising Edge Trigger)
6～17
Q0～Q11
(Qx)
O
Parallel Data Output (Nch Open Drain FET)
Latch Data
L
H
Output FET
ON
OFF
18
SO
O
Serial Data Output
19
OE
I
Output Enable Control Input
＊OE pin is pulled down to Vss.
20
VDD
-
Power Supply
●Timing chart
Fig. 7
1.
After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits into
the DATA terminal.
2.
Qx parallel output data of the shift register is set after the 12
th clock by the LCK.
3.
Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
4.
Data retained in the internal latch circuit is output when the OE is in the “L” section.
5.
The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK.
［Truth Table］
Input
Function
CLOCK
DATA
LCK
OE
×
H
All the output data output “H” with pull-up.
×
L
The Q0～Q11 output can be enable and output the data of storage register.
L
×
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
H
×
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
×
The data of shift register has no change.
SO outputs the final stage data of shift register with synchronized falling
edge of CLOCK, not controlled by OE.
×
The data of shift register is transferred to the storage register.
×
The data of storage register has no change.
＊The Q0～Q11 output have a Nch open drain Tr. The Tr is ON when data from shift register is “L”, and Tr is OFF when data is “H”.
CLOCK
LCK
DATA
DATA12
DATA11
DATA10
DATA2
DATA1
OE
Qx
Previous DATA
DATA
SO
Previous
DATA 11
Previous
DATA 11
DATA12
DATA11
“H”
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