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參數(shù)資料
| 型號： | BGB100 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | 0 dBm TrueBlue radio module |
| 中文描述： | SPECIALTY TELECOM CIRCUIT |
| 封裝： | METAL CAP, SMT-22 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 184K |
| 代理商： | BGB100 |
2002 Jan 03
6
Philips Semiconductors
Preliminary specification
0 dBm TrueBlue radio module
BGB100
Table 1
Bit allocation
Notes
1.
2.
3.
4.
5.
6.
7.
8.
In normal operation, 32 bits are programmed into the register.
bits b26 to b23 can be used for adaptive temperature compensation by the baseband.
ref: bits
‘
ref1
’
and
‘
ref0
’
define the reference frequency (see Table 3).
pwr: bits
‘
pwr1
’
and
‘
pwr0
’
define the the typical output power (see Table 4).
trx: bit
‘
trx
’
= 1 forces the IC into RX mode.
pll: bit
‘
pll
’
= 1 forces the synthesizer PLL to remain on during the entire (TX or RX) slot.
Bit b7 is the MSB of the frequency control word composed of (b7, b6, b5, b4, b3, b2, b1 and b0).
The VCO frequency is equal to 2304 + d[b7:b0] (see Table 2).
Table 2
Channel frequency programming examples
Table 3
Reference frequency programming
REGISTER BIT ALLOCATION
(1)
Data field
F
IRST
IN
b31
b30
b29
b28
b20
b26
(2)
b25
(2)
b24
(2)
b23
(2)
b22
b21
b20
b19
b18
b17
b16
see
below
0
0
0
0
0
1
0
1
0
1
0
0
0
1
1
0
L
AST
IN
see
above
b15
b14
b13
b12
b11
b10
b9
b8
b7 to b0
(7)
0
0
ref1
(3)
ref0
(3)
pwr1
(4)
pwr0
(4)
pll
(5)
trx
(6)
main divider programming
(8)
b7
b6
b5
b4
b3
b2
b1
b0
MAIN DIVIDER
RATIO
SYNTHESIZED
FREQUENCY
(MHz)
1.0
×
(2304 +n)
2402
2403
CHANNEL
FREQUENCY
Binary equivalent of n
0
0
2304 + n
2402
2403
0
0
1
1
1
1
0
0
0
0
1
1
0
1
TX channel 1
RX channel 1
TX channel 2
RX channel 78
TX channel 79
RX channel 79
1
0
1
1
0
0
0
0
2480
2480
1
0
1
1
0
0
0
1
2481
2481
b13
b12
REFERENCE DIVIDER
RATIO
REFERENCE INPUT
FREQUENCY
0
0
1
1
0
1
0
1
12
16
13
26
12 MHz
16 MHz
13 MHz
26 MHz
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