2002 Jan 03
4
Philips Semiconductors
Preliminary specification
0 dBm TrueBlue radio module
BGB100
QUICK REFERENCE DATA
V
S
= 3.0 V; T
amb
= 25
°
C; unless otherwise specified.
Note
1.
In combination with the adaptive temperature-compensation scheme provided by the baseband processor
FUNCTIONAL DESCRIPTION
Control
The BGB100 TrueBlue Bluetooth Radio Module is controlled by a baseband processor via the serial 3-wire bus. These
3 wires are data (S_DATA), clock (S_CLK) and enable (S_EN). Data sent to the device is loaded in bursts framed by
S_EN. Data and clock (S_DATA and S_CLK) signals are ignored until S_EN goes low. The programmed information is
read directly into the internal registers when S_EN goes high. S_DATA and S_EN should be stable around the rising
edges of S_CLK. There are internal pull-down resistors on all these three pins.
Only the last 32 bits serially clocked into the device are retained within the register. Additional (leading) bits are ignored,
and no check is made on the number of bits received. The data format is shown in table 1. The first data bit entered is
b31, the last one b0.
The S_EN high-to-low transition also controls the opening of the PLL. A short S_EN high pulse at the end of a time slot,
either TX or RX, serves to reset and power-down the IC. This can be omitted, at the cost of extra power consumption.
In addition to the 3-wire serial bus, there is one control signal used for accurate timing of functions within the IC, under
control by the baseband processor. This is the DCXCTR signal, to control (in RX mode) the three subsequent operating
modes of the DC compensation circuit: coarse offset estimation during the early part of the Access Code, accurate offset
estimation during the Barker sequence and the trailer, retention of the offset information during the payload.
Transmit mode
The BGB100 TrueBlue Bluetooth Radio Module contains a fully integrated transmitter function. The RF channel
frequency is selected in a conventional synthesizer, which is controlled via the serial 3-wire bus. The VCO is directly
modulated by the signal present on the T_GFSK connection. The Gaussian filtering should therefore be performed
externally. The DC bias voltage for this pin should already be present during the S_EN programming pulse, so that the
PLL can correct for possible frequency errors that might otherwise occur. Also in RX mode, this pin should be connected
to a well-defined and stable DC voltage. The robust design of the VCO makes it unnecessary to trim its freerunning
frequency. This leads to a lower component cost. A carefully designed PLL loop filter keeps frequency drift during
open-loop modulation down to a very low value.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
S
I
S1
+ I
S2
nominal supply voltage
total supply current
2.8
3
25
60
36
34
10
80
3.6
72
40
60
73
V
mA
mA
mA
mA
μ
A
dBm
during RX guard space
during demodulation
during TX guard space
during transmission
in power-down mode
BER = 0.1 % under standard
conditions
at nominal settings
Sens
receiver sensitivity
P
out
f
0
f
ref
T
amb
output power
RF frequency
reference input frequency
operating ambient temperature
(1)
4
2402
12
10
1.5
+4
2480
26
55
dBm
MHz
MHz
°
C