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參數(shù)資料
| 型號(hào)： | BGB100 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 0 dBm TrueBlue radio module |
| 中文描述： | SPECIALTY TELECOM CIRCUIT |
| 封裝： | METAL CAP, SMT-22 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 184K |
| 代理商： | BGB100 |
2002 Jan 03
12
Philips Semiconductors
Preliminary specification
0 dBm TrueBlue radio module
BGB100
Timing Parameters
Notes
1.
The S_EN signal going high switches the synthesiser on if preceded by S_DATA / S_CLK activity; the S_EN signal
going low disables the synthesizer in order to perform open-loop modulation or demodulation. Simultaneously, it
enables the receiver chain in RX mode. The length of the S_EN signal should be long enough for the synthesizer
loop to settle.
A single short S_EN pulse (without preceding S_DATA / S_CLK activity) serves to power-down the IC. It may be
omitted at the cost of increased power consumption. Any subsequent S_EN pulse without preceding
S_DATA / S_CLK activity toggles between power-up and power-down states, but brings the module into an
undefined power-up state. This mode should be avoided.
Because the VCO is directly modulated by the T_GFSK signal, the DC level on this pin should be present early on
during the synthesizer settling phase. Also in RX mode, there should be a well-defined and stable DC voltage on this
pin.
The DCXCTR signal should go high 20
μ
s before the expected end of the trailer sequence.
The DCXCTR signal should go low at the actual end of the trailer sequence. The timing for this transition should be
directly derived from the Acess Code detection algorithm inside the baseband processor.
2.
3.
4.
5.
PARAMETER
DESCRIPTION
CONDITIONS
MIN.
TYP.
2
185
2
2
2
2
20
UNIT
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
S_DATA last bit to REFCLK enable
S_EN falling edge to REFCLK disable
S_DATA last bit to S_EN rising edge
S_EN width
T_GFSK last bit to S_EN pulse start
R_DATA last bit to S_EN pulse start
S_EN pulse width
S_DATA last bit to T_GFSK DC bias
S_EN falling edge to T_GFSK first data bit
S_EN falling edge to R_DATA earliest data
bit
S_EN falling edge to DCXCTR high
DCXCTR width
0.1
0.1
180
0.1
15
note 1
note 2
note 3
t11
t12
note 4
note 5
64
20
μ
s
μ
s
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