參數(shù)資料
型號(hào)： B900J24FXX16IT
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 59.88 MHz, OTHER DSP, PQFP44
文件頁(yè)數(shù)： 85/100頁(yè)
文件大?。?/td> 1547K
代理商： B900J24FXX16IT
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
Lucent Technologies Inc.
85
8 Timing Requirements and Characteristics (continued)
8.7
Synchronous Serial Interface (SSI) Specifications (continued)
Table 107. Timing Characteristics for SSI*
* These specifications are derived from the 68HC11 specification. Some of the timing definitions may change later
to be compatible with the other timing definitions in this document.
Ref
Parameter
B900
Unit
VDD = 4.5 V to 5.5 V
VDD = 3.0 V to 3.6 V
TMIN = 12.5 ns
TMIN = 16.7 ns
Min
Max
Min
Max
t25
Master Cycle Time
2T
T is the period of CLKFREE.
—2T
—ns
Slave Cycle Time
80
—
80
—
ns
t26
Slave Enable Lead Time
5
—
5
—
ns
t27
Slave Disable Idle Time
5
—
5
—
ns
t28
Master Clock High Time
T – 25
—
T – 25
—
ns
Slave Clock High Time
40
—
40
—
ns
t29
Master Clock Low Time
T – 20
—
T – 20
—
ns
Slave Clock Low Time
40
—
40
—
ns
t30
t30 and t31 are given for slave operation. For master mode, input data setup time is 20 ns minimum and input
data hold time is still 0 ns.
Input Data Setup Time
(slave mode)
12
—
12
—
ns
t31
Input Data Hold Time
(slave mode)
0—
ns
t32
Slave Data Out Access
Time
060
0
60
ns
t33
Slave Data Out Disable
Time
012
0
12
ns
t34
Output Data Valid After
Clock
—80—80
ns
t35
Output Data Hold Time
After Clock
0—
ns
t36
Output Rise Time
1
25
1
25
ns
Input Rise Time
—
100
—
100
ns
t37
Output Fall Time
1
25
1
25
ns
Input Fall Time
—
100
—
100
ns
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