參數(shù)資料
型號： B900J24FXX16IT
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 59.88 MHz, OTHER DSP, PQFP44
文件頁數(shù)： 51/100頁
文件大小： 1547K
代理商： B900J24FXX16IT
54
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
5 Software Architecture (continued)
5.2
Register Settings (continued)
Encoding: A zero in a bit of inc disables an interrupt; a one enables the interrupt. For more information about the
Encoding: A zero in a bit of ins indicates no interrupt. A one indicates an interrupt has been recognized and is
pending or being serviced. If a one is written to bits 0, 3, 5, 8, 9, or 12 of ins (also 1 or 10 for B900), the correspond-
ing interrupt is cleared. To clear IOPA, the sbita register must be read. For more information about the fields in
Table 42. inc (Interrupt Control) Register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field
JINT*
* JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent development system tools.
SW7 SW6
SSI
—
SW5
INTB
IBFBI IOPA
SW4
TIME0 SW3 TIME1 SW2
SW1
IBF
Table 43. ins (Interrupt Status) Register
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Field JINT SW7 SW6 SSI
—
SW5
INTB IBFB IOPA SW4 TIME0 SW3 TIME1 SW2 SW1
IBF
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