參數(shù)資料
型號(hào)： AX88195P
廠商： ASIX Electronics Corporation
英文描述： 10/100BASE Local CPU Bus Fast Ethernet MAC Controller
中文描述： 一個(gè)10/100Base本地CPU總線快速以太網(wǎng)MAC控制器
文件頁(yè)數(shù)： 2/37頁(yè)
文件大?。?/td> 414K
代理商： AX88195P
ASIX ELECTRONICS CORPORATION
2
AX88195 Local CPU Bus Fast Ethernet MAC Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 4
1.1 G
ENERAL
D
ESCRIPTION
:..................................................................................................................................... 4
1.2 AX88195 B
LOCK
D
IAGRAM
:.............................................................................................................................. 4
1.3 AX88195 P
IN
C
ONNECTION
D
IAGRAM
............................................................................................................... 5
1.3.1 AX88195 Pin Connection Diagram for ISA Bus Mode................................................................................ 6
1.3.2 AX88195 Pin Connection Diagram for 80x86 Mode................................................................................... 7
1.3.3 AX88195 Pin Connection Diagram for MC68K Mode................................................................................ 8
1.3.4 AX88195 Pin Connection Diagram for MCS-51 Mode ............................................................................... 9
2.0 SIGNAL DESCRIPTION................................................................................................................................. 10
2.1 L
OCAL
CPU B
US
I
NTERFACE
S
IGNALS
G
ROUP
................................................................................................... 10
2.2 MII
INTERFACE SIGNALS GROUP
........................................................................................................................ 11
2.3 EEPROM S
IGNALS
G
ROUP
.............................................................................................................................. 12
2.4 SRAM I
NTERFACE PINS GROUP
......................................................................................................................... 12
2.5 M
ISCELLANEOUS PINS GROUP
............................................................................................................................ 12
2.6 P
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
................................................................ 13
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 14
3.1 EEPROM M
EMORY
M
APPING
.......................................................................................................................... 14
3.2 I/O M
APPING
................................................................................................................................................... 14
3.3 SRAM M
EMORY
M
APPING
.............................................................................................................................. 14
4.0 REGISTERS OPERATION............................................................................................................................. 15
4.1 C
OMMAND
R
EGISTER
(CR) O
FFSET
00H (R
EAD
/W
RITE
)................................................................................... 17
4.2 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) O
FFSET
07H (R
EAD
/W
RITE
)..................................................................... 17
4.3 I
NTERRUPT MASK REGISTER
(IMR) O
FFSET
0FH (W
RITE
)................................................................................. 18
4.4 D
ATA
C
ONFIGURATION
R
EGISTER
(DCR) O
FFSET
0EH (W
RITE
)....................................................................... 18
4.5 T
RANSMIT
C
ONFIGURATION
R
EGISTER
(TCR) O
FFSET
0DH (W
RITE
)................................................................ 18
4.6 T
RANSMIT
S
TATUS
R
EGISTER
(TSR) O
FFSET
04H (R
EAD
) ................................................................................ 19
4.7 R
ECEIVE
C
ONFIGURATION
(RCR) O
FFSET
0CH (W
RITE
) .................................................................................. 19
4.8 R
ECEIVE
S
TATUS
R
EGISTER
(RSR) O
FFSET
0CH (R
EAD
) .................................................................................. 19
4.9 I
NTER
-
FRAME GAP
(IFG) O
FFSET
16H (R
EAD
/W
RITE
) ...................................................................................... 20
4.10 I
NTER
-
FRAME GAP
S
EGMENT
1(IFGS1) O
FFSET
12H (R
EAD
/W
RITE
)............................................................... 20
4.11 I
NTER
-
FRAME GAP
S
EGMENT
2(IFGS2) O
FFSET
13H (R
EAD
/W
RITE
)............................................................... 20
4.12 MII/EEPROM M
ANAGEMENT
R
EGISTER
(MEMR) O
FFSET
14H (R
EAD
/W
RITE
).............................................. 20
4.13 T
EST
R
EGISTER
(TR) O
FFSET
15H (W
RITE
) ................................................................................................... 20
5.0 CPU I/O READ AND WRITE FUNCTIONS.................................................................................................. 21
5.1 ISA
BUS TYPE ACCESS FUNCTIONS
. ................................................................................................................... 21
5.2 80186 CPU
BUS TYPE ACCESS FUNCTIONS
......................................................................................................... 21
5.3 MC68K CPU
BUS TYPE ACCESS FUNCTIONS
...................................................................................................... 22
5.3 MCS-51 CPU
BUS TYPE ACCESS FUNCTIONS
..................................................................................................... 22
6.0 ELECTRICAL SPECIFICATION AND TIMINGS........................................................................................ 23
6.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 23
6.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 23
6.3 DC C
HARACTERISTICS
..................................................................................................................................... 23
6.4 A.C. T
IMING
C
HARACTERISTICS
....................................................................................................................... 24
6.4.1 XTAL / CLOCK........................................................................................................................................ 24
6.4.2 Reset Timing............................................................................................................................................ 24
6.4.3 ISA Bus Access Timing............................................................................................................................. 25
6.4.4 80186 Type I/O Access Timing................................................................................................................. 26
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