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參數(shù)資料
| 型號： | AX88195P |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | 10/100BASE Local CPU Bus Fast Ethernet MAC Controller |
| 中文描述： | 一個(gè)10/100Base本地CPU總線快速以太網(wǎng)MAC控制器 |
| 文件頁數(shù)： | 15/37頁 |
| 文件大小： | 414K |
| 代理商： | AX88195P |
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ASIX ELECTRONICS CORPORATION
15
AX88195 Local CPU Bus Fast Ethernet MAC Controller
4.0 Registers Operation
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS in the Command
Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
READ
00H
Command Register
( CR )
01H
Page Start Register
( PSTART )
02H
Page Stop Register
( PSTOP )
03H
Boundary Pointer
( BNRY )
04H
Transmit Status Register
( TSR )
05H
Number of Collisions Register
( NCR )
06H
Current Page Register
( CPR )
07H
Interrupt Status Register
( ISR )
08H
Current Remote DMA Address 0
( CRDA0 )
09H
Current Remote DMA Address 1
( CRDA1 )
0AH
Reserved
WRITE
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 0
Receive Configuration Register
( RCR )
Transmit Configuration Register ( TCR )
0BH
Reserved
0CH
Receive Status Register
( RSR )
Frame Alignment Errors
( CNTR0 )
CRC Errors
( CNTR1 )
Missed Packet Errors
( CNTR2 )
Data Port
0DH
0EH
Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )
Data Port
0FH
10H
11H
12H
13H
14H
15H
16H
17H
to
1EH
1FH
IFGS1
IFGS2
MII/EEPROM Access
-
Inter-frame Gap (IFG)
Reserved
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
Reserved
Reset
Reserved
Tab - 9 Page 0 of MAC Core Registers Mapping
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