參數(shù)資料
型號： AX88195P
廠商： ASIX Electronics Corporation
英文描述： 10/100BASE Local CPU Bus Fast Ethernet MAC Controller
中文描述： 一個10/100Base本地CPU總線快速以太網(wǎng)MAC控制器
文件頁數(shù)： 11/37頁
文件大?。?/td> 414K
代理商： AX88195P
ASIX ELECTRONICS CORPORATION
11
AX88195 Local CPU Bus Fast Ethernet MAC Controller
/IOCS16
OD
120
I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the
range corresponds to an I/O address to which the chip responds, and
the I/O port addressed is capable of 16-bit access.
Address Enable : The signal is asserted when the address bus is
available for DMA cycle. When negated (low), AX88195 an I/O slave
device may respond to addresses and I/O command.
PSEN : This signal is active low for 8051 program access. For I/O
device, AX88195, this signal is active high to access the chip. This
signal is for 8051 bus application only.
AEN
or
/PSEN
I/PD
124
Tab - 1 Local CPU bus interface signals group
2.2 MII interface signals group
SIGNAL
TYPE
I
PIN NO.
90 – 87
DESCRIPTION
RXD[3:0]
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
CRS
I
85
RX_DV
I
83
RX_ER
I
82
RX_CLK
I
86
COL
TX_EN
I
84
95
O
TXD[3:0]
O
99 – 96
TX_CLK
I
94
MDC
O
92
MDIO
I/O/PU
91
Tab - 2 MII interface signals group
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