參數(shù)資料
型號： AX88195P
廠商： ASIX Electronics Corporation
英文描述： 10/100BASE Local CPU Bus Fast Ethernet MAC Controller
中文描述： 一個10/100Base本地CPU總線快速以太網(wǎng)MAC控制器
文件頁數(shù)： 10/37頁
文件大?。?/td> 414K
代理商： AX88195P
ASIX ELECTRONICS CORPORATION
10
AX88195 Local CPU Bus Fast Ethernet MAC Controller
2.0 Signal Description
The following terms describe the AX88195 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
Input
Output
Input/Output
Open Drain
PU
PD
P
Pull Up
Pull Down
Power Pin
O
I/O
OD
2.1 Local CPU Bus Interface Signals Group
SIGNAL
TYPE
I/PD
PIN NO.
113 – 111
DESCRIPTION
SAL[2:0]
System Address Select Low : Signals SAL[2:0] are additional address
signal input lines which active low enable higher I/O address decoder
on chip.
System Address Select High : Signals SAH[2:0] are additional
address signal input lines which active high enable higher I/O
address decoder on chip.
System Address Select Low/High : Signals SAX[3:0] are additional
address signal input lines which active low/high depend on power on
setting to enable higher I/O address decoder on chip.
System Address : Signals SA[9:0] are address bus input lines which
lower I/O spaces on chip. SA[0] also means Upper Data Strobe
(/UDS) active low signal in 68K application mode.
Bus High Enable or Lower Data Strobe : Bus High Enable is active
low signal in some 16 bit application mode which enable high bus
(SD[15:8]) active. The signal also name as Lower Data Strobe (/LDS)
for 68K application mode.
System Data Bus : Signals SD[15:0] constitute the bi-directional
data bus.
SAH[2:0]
I/PU
116 – 114
SAX[3:0]
I/PU
122 – 121
118 – 117
SA[9:1],
SA[0]/UDS
I
10 – 1
/BHE
or
/LDS
I
18
SD[15:0]
I/O
20 – 23,
25 – 28,
30 – 33,
35 – 38
12
IREQ/IREQ
O
Interrupt Request : When ISA BUS or 80186 CPU mode is select.
IREQ is asserted high to indicate the host system that the chip
requires host software service. When MC68K or MCS-51 CPU
mode is select. /IREQ is asserted low to indicate the host system that
the chip requires host software service.
Ready : This signal is set low to insert wait states during Remote
DMA transfer.
/Dtack : When Motorola CPU type is select, the pin is active low
inform CPU that data is accepted.
Chip Select
When the /CS signal is asserted, the chip is selected.
I/O Read :The host asserts /IORD to read data from AX88195 I/O
space. When Motorola CPU type is select , the pin is useless.
I/O Write :The host asserts /IOWR to write data into AX88195 I/O
space. When Motorola CPU type is select, the pin is active high for
read operation at the same time.
RDY/DTACK
OD
125
/CS
I
123
/IORD
I
15
/IOWR
or
R/W
I
14
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