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參數(shù)資料
| 型號： | AX88140A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Fast Ethernet MAC Controller |
| 中文描述： | 快速以太網(wǎng)MAC控制器 |
| 文件頁數(shù)： | 26/46頁 |
| 文件大?。?/td> | 467K |
| 代理商： | AX88140A |
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AX88140A
PRELIMINARY
ASIX ELECTRONICS CORPORATION
26
4.2.8 Interrupt Enable Register (REG7)
1.
2.
The interrupt enable register (REG7) enables the interrupts reported by REG5.
Setting bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Field
31:17
16
R/W/C
-
R/W
Description
Reserved
NI - Normal Interrupt Summary Enable
When set, normal interrupt is enabled.
When reset, no normal interrupt is enabled. This bit (REG7<16>) enables the following bits :
CSR5<0>
CSR5<2>
CSR5<6>
CSR5<10>
CSR5<11>
AI - Abnormal Interrupt Summary Enable
When set, abnormal interrupt is enabled.
When reset, no abnormal interrupt is enabled. This bit (REG7<15>) enables the following bits :
CSR5<1>
CSR5<3>
CSR5<5>
CSR5<7>
CSR5<8>
CSR5<9>
CSR5<11>
FBE - Fatal Bus Error interrupt enable. Active high.
GPT - General purpose Timer interrupt Enable. Active high.
ETE - Early Transmit Interrupt Enable. Active high.
RW - Receive Watchdog Time out interrupt Enable. Active high
RS - Receive Stopped interrupt Enable. Active high.
RU - Receive Buffer Unavailable interrupt Enable. Active high.
RI - Receive Interrupt Enable. Active high.
UN - under-flow interrupt Enable. Active high.
Reserved.--Written as “0” for future compatibility concern.
TJ - Transmit Jabber Time out interrupt Enable. Active high.
TU - Transmit Buffer Unavailable interrupt Enable. Active high.
TS - Transmission Stopped interrupt Enable. Active high.
TI - Transmit Interrupt Enable. Active high.
Transmit interrupt
Transmit buffer unavailable
Receive interrupt
Early transmit interrupt
General-purpose timer expired
transmit process stopped
transmit jabber time-out
transmit under-flow
receive buffer unavailable
receive process stopped
receive watchdog time-out
fatal bus error
15
R/W
13
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Tab - 23 REG7 Interrupt Enable Register Description
4.2.9 Missed Frame and Overflow Counter (REG8)
Field
R/W
Description
31:29
-
Reserved
28
R/C
Overflow counter overflow
Sets When the overflow counter overflows, Resets When REG8 is read.
27:17
R/C
Overflow counter
Indicates the number of frames discarded because of overflow. The counter clears when read.
16
R/C
Missed frame overflow
Sets When the missed frame counter overflows; Resets When reg8 is read.
15:0
R/C
Missed Frame Counter
Indicates the number of frames discarded because no host receive descriptors were available. The counter
clears when read.
Tab - 24 REG8 Missed Frame and Overflow Counter Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88140AP | Fast Ethernet MAC Controller |
| AX88140AQ | Fast Ethernet MAC Controller |
| AX88196 | 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88196L | 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88140AP | 制造商:ASIX 制造商全稱:ASIX 功能描述:Fast Ethernet MAC Controller |
| AX88140AQ | 制造商:ASIX 制造商全稱:ASIX 功能描述:Fast Ethernet MAC Controller |
| AX88141 | 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX PCI BUS FAST ETHERNET MAC CONTROLLER WITH POWER MANAGEMENT |
| AX88170L | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to Fast Ethernet/HomePNA Controller |
| AX88172 | 制造商:ASI 制造商全稱:ASI 功能描述:USB2.0 TO ETHERNET Device setup guide |
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