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參數(shù)資料
| 型號： | AX88140A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Fast Ethernet MAC Controller |
| 中文描述： | 快速以太網(wǎng)MAC控制器 |
| 文件頁數(shù)： | 21/46頁 |
| 文件大?。?/td> | 467K |
| 代理商： | AX88140A |
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AX88140A
PRELIMINARY
ASIX ELECTRONICS CORPORATION
21
4.2 Host REGs
4.2.1 Bus Mode Register (REG0)
FIELD
31:22
21
R/W/C
-
R/W
DESCRIPTION
RESERVED
RML - Read Multiple
When set, the AX88140A supports the memory-read-multiple command on the PCI bus. This bus
command is used in memory read bursts with more than one longword. When reset, the AX88140A
uses memory-read command in all its memory read accesses on the PCI bus.
DBO - Descriptor Byte Ordering Mode
When set, the AX88140A operates in big edian ordering mode for descriptors only.
When reset, the AX88140A operates in little endian mode.
Reserved.--Written as “0” for future compatibility concern.
PBL - Programmable Burst Length
Indicates the maximum number of longwords to be transfered in one DMA transaction. If reset, the
ax88140a burst is limitedonlybythe amountof data storedin the receive FIFO(at least 16longword),
or bythe amountof freespace inthe transmitFIFO (atleast 16longword) beforeissuing abusrequest.
The PBL can be programmed with permissible values 0,1,2,4,8,16, or 32. After reset, the PBL default
value is 0.
BLE - Big/Little Endian
When set, the AX88140A operates in big endian byte ordering mode. When reset, the AX88140A
operates in little endian byte ordering mode. Big endian is applicable only for data buffer
RESERVED
BAR - Bus Arbitration
Selects the internal bus arbitration between the receive and transmit processes.
When set, a round robin arbitration scheme is applied resulting in equal sharing between processes.
Whenreset,thereceiveprocesshaspriorityoverthetransmitprocess,unlesstheax88140aiscurrently
transmitting.
SWR - Software Reset
When set, the AX88140A resets all internal hardware with the exception of the configuration area and
also, it does not change the port select setting (REG6<18>).
Software reset does not affect the configuration area.
20
R/W
19:14
13:8
-
R/W
7
R/W
6:2
1
-
R/W
0
R/W
Tab - 15 REG0 Bus Mode Register Description
4.2.2 Transmit Poll Demand (REG1)
FIELD
R/W
31:0
W
TPD - Transmit Poll Demand
When written with any value, the AX88140A checks for frames to be transmitted. If no descriptor is
available, the transmit process returns to the suspended states and REG5<2> is asserted. If the descriptor
is available the transmit process resumes.
DESCRIPTION
Tab - 16 REG1 Transmit Poll Demand Register Description
相關PDF資料 |
PDF描述 |
|---|---|
| AX88140AP | Fast Ethernet MAC Controller |
| AX88140AQ | Fast Ethernet MAC Controller |
| AX88196 | 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88196L | 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88796 | 3-in-1 Local Bus Fast Ethernet Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AX88140AP | 制造商:ASIX 制造商全稱:ASIX 功能描述:Fast Ethernet MAC Controller |
| AX88140AQ | 制造商:ASIX 制造商全稱:ASIX 功能描述:Fast Ethernet MAC Controller |
| AX88141 | 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX PCI BUS FAST ETHERNET MAC CONTROLLER WITH POWER MANAGEMENT |
| AX88170L | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to Fast Ethernet/HomePNA Controller |
| AX88172 | 制造商:ASI 制造商全稱:ASI 功能描述:USB2.0 TO ETHERNET Device setup guide |
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