參數(shù)資料
型號(hào)： AU1100LCDPERF_30274A
英文描述： AMD Alchemy? SolutionsAu1100? Processor LCD Performance Application Note? 574KB (PDF)
中文描述： 采用AMD Alchemy？ SolutionsAu1100？處理器液晶性能應(yīng)用筆記？ 574KB（PDF格式）
文件頁(yè)數(shù)： 6/19頁(yè)
文件大?。?/td> 574K
代理商： AU1100LCDPERF_30274A
6
Application Note
Rev. 30274A April 2003
AMD Alchemy Solutions Au1100 Processor LCD Performance
The illustration also demonstrates the impact of transfer time on latency, and in turn bandwidth.
While the transfer time to integrated peripheral registers is negligible, the SDRAM, and Static Bus
transfer times can add appreciable delay to system bus latency.
Note that from the perspective of system bus master X, increases in system bus latency result in fewer
opportunities for system bus master X to perform transfers to/from SDRAM in a given time interval.
Thus an increase in system bus latency results in a decrease in effective SDRAM bandwidth for
system bus master X (the actual SDRAM bandwidth potential is unchanged, as outlined in the
SDRAM applications note).
3.2.1 SDRAM Interface
For a 396MHz Au1100 processor operating the SDRAM controller at 99MHz, an SDRAM single-
beat access is 60ns (6 cycles at 10.1ns), and an SDRAM burst access is 121ns (12 cycles at 10.1ns).
Accesses to SDRAM can add upwards to 121ns to the system bus latency for other system bus
masters.
A typical SDRAM configuration is capable of approximately 248.9MB/s throughput. The SDRAM
bandwidth is important since it is the main storage for applications, data and the LCD framebuffer.
There must be enough SDRAM bandwidth to satisfy the LCD controller refresh demand as well as
run the applications.
The SDRAM bandwidth needed by the LCD controller is a product of the display resolution size,
pixel depth and refresh rate. The following table lists some common resolutions and the resulting
SDRAM bandwidth requirement.
The above values represent the SDRAM bandwidth demand of the LCD controller as it continuously
refreshes the display. With a total SDRAM bandwidth of 248.9MB/s, the LCD controller consumes a
relatively small percentage, leaving ample bandwidth for the Au1 core to run applications and
perform graphics operations.
The LCD controller timing values should be configured so as to minimize the SDRAM bandwidth
demand. In particular, the refresh rate should be set to the lowest rate permitted by the display.
Table 1: LCD Controller SDRAM Bandwidth
Horizontal
(Pixels)
Vertical
(Pixels)
Depth
(Bits Per
Pixel)
Refresh
Rate
(Hz)
Bandwidth
(MB/s)
QVGA
320
240
8
60
4.6MB/s
QVGA
320
240
16
60
9.2MB/s
VGA
640
480
16
60
36.8MB/s
XGA
800
600
16
60
57.6MB/s
XGA
800
600
16
72
69.1MB/s
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