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| 型號(hào)： | AU1100LCDPERF_30274A |
| 英文描述： | AMD Alchemy? SolutionsAu1100? Processor LCD Performance Application Note? 574KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1100？處理器液晶性能應(yīng)用筆記？ 574KB（PDF格式） |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大小： | 574K |
| 代理商： | AU1100LCDPERF_30274A |
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Application Note
13
AMD Alchemy Solutions Au1100 Processor LCD Performance
Rev. 30274A April 2003
The lcd_control[22:21]=11b (4 SDRAM burst per arbitration) significantly increases the chances of
the LCD controller filling a 320-word buffer in the allotted time.
While this table indicates that it is possible to avoid under-flow in all situations, keep in mind that this
does not include system bus accesses by other masters, or PCMCIA (or static bus) transfers with
transfer times greater than 600ns. The presence of more system bus requestors or longer PCMCIA
transfer times increases the likelihood of a buffer under-flow, and the undesirable display artifacts.
4.1.2 LCD Controller sys_powerctrl[17] Setting
To further combat the effects of system bus latency, the Au1100 processor (stepping BE and newer)
features a setting in sys_powerctrl[17] to change the system bus arbitration scheme in favor of the
LCD controller. Setting sys_powerctrl[17] to 1 gives the LCD controller priority over other system
bus requestors.
Figure 4: System Bus Arbitration with sys_powerctrl[17]=1
The change in the arbitration scheme permits shorter system bus latency for the LCD controller, and
therefore more opportunities onto the system bus which in turn increases the likelihood of filling the
320-word buffer on time.
Note that this setting does not allow the LCD controller unconditional access to the system bus. The
LCD controller must still wait if another system bus master is using the system bus. It does, however,
reduce the number of arbitration cycles needed for the LCD controller to win the system bus. The end
result is that the system bus latency for the LCD controller decreases, while the latency for the other
bus masters slightly increases.
This setting is likely to help LCD display refresh in a system where many peripherals are requesting
the system bus, but may not help when the Au1 core is accessing slow PCMCIA cards during the fill
of the 320-word buffer.
600ns
(PWAIT# asserted)
6,000ns
4,840ns
10,840ns
Table 8: PCMCIA and LCD Transfer Times with lcd_control[22:21]=11b
PCMCIA Transfer Time
10 PCMCIA Accesses
40 SDRAM Accesses
PCMCIA +LCD Time
LCD
A
B
CX
Req A
Req B
Req C
LCD
SBUS
LCD
LCD
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