參數(shù)資料
型號(hào)： AU1100LCDPERF_30274A
英文描述： AMD Alchemy? SolutionsAu1100? Processor LCD Performance Application Note? 574KB (PDF)
中文描述： 采用AMD Alchemy？ SolutionsAu1100？處理器液晶性能應(yīng)用筆記？ 574KB（PDF格式）
文件頁(yè)數(shù)： 4/19頁(yè)
文件大?。?/td> 574K
代理商： AU1100LCDPERF_30274A
4
Application Note
Rev. 30274A April 2003
AMD Alchemy Solutions Au1100 Processor LCD Performance
The performance of any input/output peripheral is usually described in terms of the maximum amount
of data that can be moved through the interface in a given time period. For example, a 100Mbps
Ethernet controller can move a maximum of 12.5MB/s. If the actual performance is less than the
maximum, data movement occurs at a slower pace.
In the case of the output-only LCD controller, the performance is essentially a constant. Unlike many
peripheral I/Os, if the LCD controller fails to satisfy the constant performance requirement, the
display refresh fails, resulting in visual artifacts (and not just slower data movement).
The performance constant for the LCD controller is easily calculated for a given display type.
However, the LCD controller is only one aspect of performance in an Au1100 processor based design.
The remainder of this document identifies influences on the system performance of a design using the
Au1100 processor LCD.
3.0 Unified Memory Architecture Fundamentals
Figure 1: “Au1100 Processor LCD controller” depicts a unified memory architecture (UMA)
arrangement where the memory used by the LCD controller for the framebuffer is shared with the rest
of the system. In this arrangement, the Au1 core performs all drawing in the framebuffer, which
resides in SDRAM, and the LCD controller continuously refreshes the display by fetching the
framebuffer contents and sending the pixel data to the display.
In a non-unified memory architecture, the LCD (or graphics) controller has a dedicated memory pool
that contains the framebuffer. Furthermore, the LCD (or graphics) controller has priority over
processor-initiated accesses to the framebuffer memory in order to maintain the refresh of the display.
By eliminating the need for a dedicated framebuffer memory pool, a UMA is a more cost-effective
graphics solution than a non-unified memory architecture environment. However, since the Au1 core,
LCD controller and other peripherals share the SDRAM, memory latency and bandwidth can affect
system performance.
3.1 System Bus (SBUS)
The system bus (SBUS) is the main bus within the Au1100 processor. As such, access to the system
bus is necessary in order to access the SDRAM, the Static Bus, or the integrated peripherals.
The SBUS typically operates at one-half the Au1 core frequency, and the SDRAM controller operates
at one-half the frequency of the SBUS.
The Au1100 processor SBUS has four bus master slots for handling six system bus masters:
Au1 core
Ethernet MAC controller and DMA controller
USB Host controller and IrDA controller
LCD controller
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