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參數(shù)資料
| 型號： | AU1100LCDPERF_30274A |
| 英文描述： | AMD Alchemy? SolutionsAu1100? Processor LCD Performance Application Note? 574KB (PDF) |
| 中文描述： | 采用AMD Alchemy？ SolutionsAu1100？處理器液晶性能應(yīng)用筆記？ 574KB（PDF格式） |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 574K |
| 代理商： | AU1100LCDPERF_30274A |
Application Note
5
AMD Alchemy Solutions Au1100 Processor LCD Performance
Rev. 30274A April 2003
The arbitration scheme for the system bus is round-robin; each bus master slot has equal opportunity
to obtain access to the system bus. For a particular system bus master X, if no other system bus
masters request the bus, then bus master X immediately wins the system bus. By contrast, if all other
system bus masters request the bus, then bus master X must wait for three other system bus master
slots’ transfers before it wins the system bus, as depicted in the following figure.
Figure 2: System Bus Arbitration
When a system bus master wins arbitration of the system bus, it performs transfers to/from the
integrated peripherals, SDRAM, or the Static bus.
3.2 Latency and Bandwidth
Latency is defined as the amount of time between when a request for a resource is initiated and when
the request for that resource is granted. In the scope of this discussion, latency is the time between
when a system bus master (e.g. LCD controller) requests access to the system bus (e.g. in order to
access framebuffer memory) and when the system bus is granted to that master. Bandwidth is the
amount of data that can be moved across the system bus in a time interval. In the Au1100, latency and
bandwidth are inversely related such that an increase in latency results in a decrease in bandwidth
(since less time is available to move data), and vice versa.
Two factors influence latency and bandwidth: system bus arbitration, and transfer time.
As stated previously, access to SDRAM requires access to the system bus. For all practical purposes,
the latency onto the system bus is the latency to the SDRAM. Figure 3: “System Bus Latency for a
Bus Master” illustrates the round-robin arbitration scheme with all system bus masters requesting the
bus simultaneously, and the corresponding effect on system bus latency for bus master X.
Figure 3: System Bus Latency for a Bus Master
A
B
C
X
Req A
Req B
Req C
Req X
SBUS
A
B
C
X
Req A
Req B
Req C
Req X
SBUS
Latency for System Bus Master X
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AU1100-MOBILE-RDK | 制造商:Advanced Micro Devices 功能描述: |
| AU1100-WH-V1 | 制造商:Pass & Seymour/Legrand 功能描述:SPEAKER LEVEL 4 LOC SELECTOR KIT WH |
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