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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATUC128D4-AUR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 451/755闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 128KB FLASH 48TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 2,500
绯诲垪锛� AVR®32 UC3 D
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 32-浣�
閫熷害锛� 48MHz
閫i€氭€э細 I²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孌MA锛孖²S锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 35
绋嬪簭瀛樺劜鍣ㄥ閲忥細 128KB锛�128K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 16K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.65 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 6x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 48-TQFP
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATUC128D4-AUR-ND
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�
504
32133D鈥�11/2011
UC3D
25. Pulse Width Modulation Controller (PWMA)
Rev: 2.0.0.0
25.1 Features
Left-aligned non-inverted 12-bit PWM
Common 12-bit timebase counter
鈥� Asynchronous clock source supported
鈥� Spread-spectrum counter to allow a constantly varying duty cycle
Separate 12-bit duty cycle register per channel
Synchronized channel updates
鈥� No glitches when changing the duty cycles
Interlinked operation supported
鈥� Up to 32 channels can be updated with the same duty cycle value at a time
鈥� Up to 4 channels can be updated with different duty cycle values at a time
Interrupt on PWM timebase overflow
Output PWM waveforms
鈥� Support normal waveform output for each channel
鈥� Support composite waveform generation (XOR鈥檈d) for each pair channels
25.2 Overview
The Pulse Width Modulation Controller (PWMA) controls several pulse width modulation (PWM)
channels. The number of channels is specific to the device. Each channel controls one square
output PWM waveform. Characteristics of the output PWM waveforms such as period and duty
cycle are configured through the user interface. All user interface registers are mapped on the
peripheral bus.
The duty cycle value for each channel can be set independently, while the period is determined
by a common timebase counter (TC). The timebase for the counter is selected by using the allo-
cated asynchronous Generic Clock (GCLK). The user interface for the PWMA contains
handshake and synchronizing logic to ensure that no glitches occur on the output PWM wave-
forms while changing the duty cycle values.
PWMA duty cycle values can be changed using two approaches, either an interlinked single-
value mode or an interlinked multi-value mode. In the interlinked single-value mode, any set of
channels, up to 32 channels, can be updated simultaneously with the same value while the other
channels remain unchanged. There is also an interlinked multi-value mode, where the 8 least
significant bits of up to 4 channels can be updated with 4 different values while the other chan-
nels remain unchanged.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-B72-IW-F2 CONVERTER MOD DC/DC 15V 100W
V24C12H150B2 CONVERTER MOD DC/DC 12V 150W
VI-B71-IX-F3 CONVERTER MOD DC/DC 12V 75W
VI-B71-IX-F2 CONVERTER MOD DC/DC 12V 75W
VI-B71-IX-F1 CONVERTER MOD DC/DC 12V 75W
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ATUC128D4-AUT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATUC128D4-Z1UR 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATUC128D4-Z1UT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATUC128L3U-AUR 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3L-128KB Flash 64QFP 85C green T&R RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATUC128L3U-AUT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3L-128KB Flash 64QFP 85C green TRAY RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT