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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATUC128D4-AUR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 218/755闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 128KB FLASH 48TQFP
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鏍稿績铏曠悊鍣細 AVR
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 16K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.65 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 6x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
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灏佽/澶栨锛� 48-TQFP
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATUC128D4-AUR-ND
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29闋�绗�730闋�绗�731闋�绗�732闋�绗�733闋�绗�734闋�绗�735闋�绗�736闋�绗�737闋�绗�738闋�绗�739闋�绗�740闋�绗�741闋�绗�742闋�绗�743闋�绗�744闋�绗�745闋�绗�746闋�绗�747闋�绗�748闋�绗�749闋�绗�750闋�绗�751闋�绗�752闋�绗�753闋�绗�754闋�绗�755闋�
295
32133D鈥�11/2011
UC3D
19.6.2.12
Multi packet mode and single packet mode.
Single packet mode is the default mode where one USB packet is managed per bank.
The multi-packet mode allows the user to manage data exceeding the maximum endpoint size
(UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention.
This mode can also be coupled with the ping-pong mode.
For an OUT endpoint, the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE field should be
configured correctly to enable the multi-packet mode. See 鈥滿ulti packet mode for OUT
endpoints鈥� on page 300. For single packet mode, the MULTI_PACKET_SIZE should be
initialized to 0.
For an IN endpoint, the EPn_PCKSIZE_BK0/1.BYTE_COUNT field should be configured
correctly to enable the multi-packet mode. See鈥滿ulti packet mode for IN endpoints鈥� on page
298. For single packet mode, the BYTE_COUNT should be less than EPSIZE.
19.6.2.13
Management of control endpoints
Overview
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn is irrelevant for control endpoints. The user should
therefore never use it for these endpoints. When read, this value is always zero.
Control endpoints are managed using:
The RXSTPI bit: is set when a new SETUP packet is received. This has to be cleared by
firmware in order to acknowledge the packet and to free the bank.
The RXOUTI bit: is set when a new OUT packet is received. This has to be cleared by
firmware in order to acknowledge the packet and to free the bank.
The Transmitted IN Data Interrupt (TXINI) bit: is set when the current bank is ready to accept
a new IN packet. This has to be cleared by firmware in order to send the packet.
Control write
Figure 19-6 on page 296 shows a control write transaction. During the status stage, the control-
ler will not necessarily send a NAK on the first IN token:
If the user knows the exact number of descriptor bytes that will be read, the status stage can
be predicted, and a zero-length packet can be sent after the next IN token.
Alternatively the bytes can be read until the NAKed IN Interrupt (NAKINI) is triggered,
notifying that all bytes are sent by the host and that the transaction is now in the status stage.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-B72-IW-F2 CONVERTER MOD DC/DC 15V 100W
V24C12H150B2 CONVERTER MOD DC/DC 12V 150W
VI-B71-IX-F3 CONVERTER MOD DC/DC 12V 75W
VI-B71-IX-F2 CONVERTER MOD DC/DC 12V 75W
VI-B71-IX-F1 CONVERTER MOD DC/DC 12V 75W
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ATUC128D4-Z1UR 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATUC128D4-Z1UT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3D4 128KB FL 85C RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATUC128L3U-AUR 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3L-128KB Flash 64QFP 85C green T&R RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATUC128L3U-AUT 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU UC3L-128KB Flash 64QFP 85C green TRAY RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT