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參數(shù)資料
| 型號(hào)： | ATF1500 |
| 廠商： | Atmel Corp. |
| 英文描述： | 44-pin Complex PLD(44腳復(fù)雜可編程邏輯器件) |
| 中文描述： | 44引腳復(fù)雜可編程邏輯器件（44腳復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 195K |
| 代理商： | ATF1500 |
Flash PLD
4
Figure 5.
Memory and I/O Interface Design in the ATF1500
Key Device Features Utilized in the Memory and I/O Interface Design
The following lists the key device features that allowed this
Memory and I/O Interface design example to fit efficiently in
an ATF1500 device.
1.
Global Connectivity of the ATF1500: The capability
of the ATF1500 to provide 100% connectivity
between all macrocells allows both the 19-bit and
8-bit Address and Data busses to be routed
throughout the device. This feature eliminates any
routing bottlenecks and efficiently utilizes all device
resources for logic implementation. Due to the high
interconnectivity between the three logic blocks
(ADDRCNTR, DATAMUX and SWLATCH blocks),
this design would not fit if global connectivity were
not available.
2.
Output Enable Product Term for each I/O: As shown
in Figure 5, the design required an output enable
product term for the OE control of the bi-directional
DATA pins. If output enable product terms are not
available, then two pins (an input and an I/O pin) will
be needed to generate the output enable control
logic, i.e. externally wiring the output pin to the input
pin. The two additional pins would have prevented
the design from fitting into the ATF1500 because all
36 input and I/O pins were used in the design.
3.
Latch Configuration for the Macrocell Register:
Each register of the ATF1500 macrocell can be con-
figured as a transparent latch. In the Memory and
I/O Interface design, five latches were needed to
latch the keypad data.
4.
Buried Feedback Path from each Macrocell: The
buried feedback paths of the ATF1500 macrocells
allowed the macrocell logic to be used even when
the I/O pins associated with these macrocells are
configured as inputs for the Keypad signals.
Bus Friendly Pin-keeper Circuits: The bus-friendly
“
pin-keeper
”
circuits on the ATF1500 Input and I/O
pins eliminated the need of external pull-up resis-
tors on the bi-directional DATA pins (connected to
the 8-bit Data bus).
Acknowledgment: This Memory and I/O Interface design
was contributed by Jim Millener of JCM II, Inc.
5.
Summary
The ATF1500 is a high-performance, high-density Flash-
based Complex PLD. It has flexible macrocells that are glo-
bally connected, and a variety of speed and power
management features. It is available in a 44-lead PLCC or
TQFP package. For software support, Atmel provides a fit-
ter that interfaces with ABEL, CUPL and Synario tools. For
converting existing designs, Atmel provides the POF2JED
utility that reads a POF programming file and creates an
ATF1500 JEDEC file.
I_44
*
I_14
I_6
BUF[18:0]
*
I_11
*
I_10
*
I_12
*
I_35
*
I_33
*
I_34
*
I_36
*
I_8
*
BI[7:0]
*
I_4
SWLATCH
Key0
Key1
Key3
Latch
MuxOut[7-0]
I_5
ADDRCNTR
AddrOut[18-0]
AddSel0
AddSel1
Clock
DataBus[7-0]
Enable
Reset
I_2
DATAMUX
Addr[18-0]
Din[7-0]
S0
S1
Dout[7-0]
Enter
E
Up
DataOut[7:0]
SwData[7:0]
Key0
Key1
Key2
Key4
Down
Right
Data[7:0]
Left
Address[18:0]
Clock
DataIn[7:0]
A[18:0]
R_W
R_W_in
R_W_inN
RS0
Reg0
RS1
Reg1
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| ATF1500-7AC | 制造商:Atmel Corporation 功能描述: |
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