參數(shù)資料
型號: ATAM893T-TKQ
廠商: Atmel
文件頁數(shù): 45/98頁
文件大?。?/td> 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標準包裝: 4,000
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
5
4680C–4BMCU–01/05
ATAM893-D
4.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction
decoder and interrupt controller. The following sections describe each functional block in more
detail.
4.2.1
Program Memory
The program memory (EEPROM) is programmable with the customer application program. The
EEPROM is addressed by a 12-bit wide program counter, thus predefining a maximum program
bank size of 4 Kbytes. The lowest user program memory address segment is taken up by a 512-
byte zero page which contains predefined start addresses for interrupt service routines and spe-
cial subroutines accessible with single byte instructions (SCALL).
The corresponding memory map is shown in Figure 4-2. Look-up tables of constants can 0also
be held in ROM and are accessed via the MARC4’s built-in table instruction.
Figure 4-2.
ROM Map
4.2.2
RAM
The ATAM893-D contains 256
× 4-bit wide static random access memory (RAM). It is used for
the expression stack, the return stack and data memory for variables and arrays. The RAM is
addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y.
4.2.2.1
Expression Stack
The 4-bit wide expression stack is addressed with the expression Stack Pointer (SP). All arith-
metic, I/O and memory reference operations take their operands from, and return their results to
the expression stack. The MARC4 performs the operations with the top of stack items (TOS and
TOS-1). The TOS register contains the top element of the expression stack and works in the
same way as an accumulator. This stack is also used for passing parameters between subrou-
tines and as a scratch pad area for temporary storage of data.
EEPROM
(4 K x 8 bit)
Zero page
FFFh
7FFh
1FFh
000h
1F0h
1F8h
010h
018h
000h
008h
020h
1E8h
1E0h
S
C
A
LL
addresses
140h
180h
040h
0C 0h
008h
$AUTOSLEEP
$RESET
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
1E0h
1C 0h
100h
080h
page
000h
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