參數(shù)資料
型號(hào): AT91SAM7S32B-MU
廠商: Atmel
文件頁數(shù): 38/165頁
文件大?。?/td> 0K
描述: IC MCU ARM7 32KB FLASH 48-VQFN
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 250
系列: SAM7S
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 55MHz
連通性: I²C,SPI,SSC,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 托盤
配用: AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
132
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock
bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of
the lock region using a Flash write and lock command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.
20.2.5.3
Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the
erase command is aborted and no page is erased.
20.2.5.4
Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the com-
mand. When bit 0 of the bit mask is set, then the first lock bit is activated.
In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the
EA command.
...
n
Write handshaking
ADDR0
Memory Address LSB
n+1
Write handshaking
ADDR1
Memory Address
n+2
Write handshaking
ADDR2
Memory Address
n+3
Write handshaking
ADDR3
Memory Address
n+4
Write handshaking
DATA
*Memory Address++
n+5
Write handshaking
DATA
*Memory Address++
...
Table 20-9.
Write Command (Continued)
Step
Handshake Sequence
MODE[3:0]
DATA[7:0]
Table 20-10. Full Erase Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0] or DATA[7:0]
1
Write handshaking
CMDE
EA
2
Write handshaking
DATA
0
Table 20-11. Set and Clear Lock Bit Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0] or DATA[7:0]
1
Write handshaking
CMDE
SLB or CLB
2
Write handshaking
DATA
Bit Mask
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