參數(shù)資料
型號： AT91SAM7S32B-MU
廠商： Atmel
文件頁數(shù)： 128/165頁
文件大?。?/td> 0K
描述： IC MCU ARM7 32KB FLASH 48-VQFN
產品培訓模塊： MCU Product Line Introduction
標準包裝： 250
系列： SAM7S
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 55MHz
連通性： I²C，SPI，SSC，UART/USART
外圍設備： 欠壓檢測/復位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 1.65 V ~ 1.95 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 48-VFQFN 裸露焊盤
包裝： 托盤
配用： AT91SAM-ICE-ND - EMULATOR FOR AT91 ARM7/ARM9
AT91SAM7S-EK-ND - KIT EVAL FOR ARM AT91SAM7S
65
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
13.3.5
Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in descend-
ing order:
Power-up Reset
Brownout Reset
Watchdog Reset
Software Reset
User Reset
Particular cases are listed below:
When in User Reset:
– A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
– A software reset is impossible, since the processor reset is being activated.
When in Software Reset:
– A watchdog event has priority over the current state.
– The NRST has no effect.
When in Watchdog Reset:
– The processor reset is active and so a Software Reset cannot be programmed.
– A User Reset cannot be entered.
13.3.6
Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software
reset should be performed until the end of the current one. This bit is automatically cleared at the end of the
current software reset.
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising
edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This
transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-9). If the User Reset is
disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the
URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the
interrupt.
BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It
triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR
register resets the BODSTS bit and clears the interrupt.
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