參數(shù)資料
型號(hào)： AT90S4433-8AC
廠商： Atmel
文件頁數(shù)： 60/126頁
文件大?。?/td> 0K
描述： IC MCU 4K FLSH 8MHZ A/D 32TQFP
標(biāo)準(zhǔn)包裝： 250
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 4KB（2K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x10b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 32-TQFP
包裝： 托盤
39
AT90S/LS4433
1042H–AVR–04/03
Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1, and 0
The Clock Select1 bits 2, 1, and 0 define the prescaling source of Timer/Counter1.
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes
are scaled directly from the CK Oscillator clock. If the external pin modes are used for
Timer/Counter0, transitions on PD5/(T1) will clock the counter even if the pin is config-
ured as an output. This feature can give the user software control of the counting.
Timer/Counter1 – TCNT1H and
TCNT1L
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To
ensure that both the High and Low Bytes are read and written simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary regis-
ter (TEMP). This temporary register is also used when accessing OCR1 and ICR1. If the
main program and interrupt routines perform access to registers using TEMP, interrupts
must be disabled during access from the main program (and from interrupt routines if
interrupts are allowed from within interrupt routines).
TCNT1 Timer/Counter1 Write
When the CPU writes to the High Byte TCNT1H, the written data is placed in the TEMP
Register. Next, when the CPU writes the Low Byte TCNT1L, this byte of data is com-
bined with the byte data in the TEMP Register, and all 16 bits are written to the TCNT1
Timer/Counter1 Register simultaneously. Consequently, the High Byte TCNT1H must
be accessed first for a full 16-bit register write operation.
TCNT1 Timer/Counter1 Read
When the CPU reads the Low Byte TCNT1L, the data of the Low Byte TCNT1L is sent
to the CPU and the data of the High Byte TCNT1H is placed in the TEMP Register.
When the CPU reads the data in the High Byte TCNT1H, the CPU receives the data in
Table 12. Clock 1 Prescale Select
CS12
CS11
CS10
Description
0
Stop, the Timer/Counter1 is stopped.
001
CK
010
CK/8
011
CK/64
100
CK/256
101
CK/1024
1
0
External Pin T1, falling edge
1
External Pin T1, rising edge
Bit
15141312
11
10
9
8
$2D ($4D)
MSB
TCNT1H
$2C ($4C)
LSB
TCNT1L
76
543
210
Read/Write
R/W
R/WR/W
Initial Value
0
00
000
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