參數(shù)資料
型號(hào): AT90S4433-8AC
廠商: Atmel
文件頁(yè)數(shù): 47/126頁(yè)
文件大小: 0K
描述: IC MCU 4K FLSH 8MHZ A/D 32TQFP
標(biāo)準(zhǔn)包裝: 250
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 4KB(2K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 32-TQFP
包裝: 托盤
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27
AT90S/LS4433
1042H–AVR–04/03
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine or restored when returning from an interrupt routine. This must be handled by
software.
General Interrupt Mask
Register – GIMSK
Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU General Control Register (MCUCR) defines whether the External
Interrupt is activated on rising or falling edge of the INT1 pin or is level sensed. Please
note that INTF1 Flag is not set when the level-sensitive interrupt condition is met. How-
ever, INT1 interrupt is generated, provided that INT1 mask bit is set in GIMSK Register.
Activity on the pin will cause an interrupt request even if INT1 is configured as an output.
The corresponding interrupt of External Interrupt Request 1 is executed from program
memory address $002. See also “External Interrupts”.
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU General Control Register (MCUCR) defines whether the External
Interrupt is activated on rising or falling edge of the INT0 pin or is level sensed. Please
note that INTF0 Flag is not set when the level-sensitive interrupt condition is met. How-
ever, INT0 interrupt is generated, provided that INT0 mask bit is set in GIMSK Register.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from program
memory address $001. See also “External Interrupts”.
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and always read as zero.
General Interrupt Flag
Register – GIFR
Bit 7 – INTF1: External Interrupt Flag1
When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt
flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT1 in GIMSK, is set (one), the MCU will jump to the Interrupt Vector. The
flag is always cleared when the interrupt routine is executed. Alternatively, the flag is
cleared by writing a logical “1” to it. This flag is always cleared when INT1 is configured
as level interrupt.
Bit
7
6
5
4
3
2
1
0
$3B ($5B)
INT1
INT0
GIMSK
Read/Write
R/W
R
Initial Value
0
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
INTF1
INTF0
GIFR
Read/Write
R/W
R
Initial Value
0
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