參數(shù)資料
型號: AT90S4433-8AC
廠商: Atmel
文件頁數(shù): 57/126頁
文件大?。?/td> 0K
描述: IC MCU 4K FLSH 8MHZ A/D 32TQFP
標準包裝: 250
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 32-TQFP
包裝: 托盤
36
AT90S/LS4433
1042H–AVR–04/03
Interrupt Flag Register (TIFR). The interrupt enable/disable settings for Timer/Counter1
are found in the Timer/Counter Interrupt Mask Register (TIMSK).
When Timer/Counter1 is externally clocked, the external signal is synchronized with the
Oscillator frequency of the CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
clock period. The external clock signal is sampled on the rising edge of the internal CPU
clock.
The 16-bit Timer/Counter1 features both a high resolution and a high-accuracy usage
with the lower prescaling opportunities. Similarly, the high prescaling opportunities
makes the Timer/Counter1 useful for lower speed functions or exact timing functions
with infrequent actions.
The Timer/Counter1 supports an Output Compare function using the Output Compare
Register1 (OCR1) as the data source to be compared to the Timer/Counter1 contents.
The Output Compare functions include optional clearing of the counter on compare
matches and actions on the Output Compare pin 1 on compare matches.
Timer/Counter1 can also be used as a 8-, 9-, or 10-bit Pulse Width Modulator. In this
mode, the counter and the OCR1 Register serve as a glitch-free, stand-alone PWM with
centered pulses. Refer to page 41 for a detailed description of this function.
The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1
contents to the Input Capture Register (ICR1), triggered by an external event on the
Input Capture Pin (ICP). The actual capture event settings are defined by the
Timer/Counter1 Control Register (TCCR1). In addition, the Analog Comparator can be
set to trigger the Input Capture. Refer to the section, “The Analog Comparator”, for
details of this. The ICP pin logic is shown in Figure 33.
Figure 33. ICP Pin Schematic Diagram
If the Noise Canceler function is enabled, the actual trigger condition for the capture
event is monitored over four samples, and all four must be equal to activate the Capture
Flag. The input pin signal is sampled at XTAL clock frequency.
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