參數(shù)資料
型號: AT90LS8535-4AI
廠商: Atmel
文件頁數(shù): 94/127頁
文件大?。?/td> 0K
描述: IC MCU 8K 4MHZ A/D LV IT 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: AVR® 90LS
核心處理器: AVR
芯體尺寸: 8-位
速度: 4MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
1997 Microchip Technology Inc.
DS30272A-page 69
PIC16C71X
9.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which species the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 9-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 9-1
shows the opcode eld descriptions.
For byte-oriented instructions, 'f' represents a le reg-
ister designator and 'd' represents a destination desig-
nator. The le register designator species which le
register is to be used by the instruction.
The destination designator species where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the le register specied in the instruction.
For bit-oriented instructions, 'b' represents a bit eld
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
le in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 9-1:
OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories:
Field
Description
f
Register le address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit le register
k
Literal eld, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in le register f.
Default is d = 1
label
Label name
TOS
Top of Stack
PC
Program Counter
PCLATH
Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Time-out bit
PD
Power-down bit
dest
Destination either the W register or the specied
register le location
[ ]
Options
( )
Contents
Assigned to
< >
Register bit eld
In the set of
italics User dened term (font is courier)
Byte-oriented operations
Bit-oriented operations
Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1
s. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2
s.
Table 9-2 lists the instructions recognized by the
MPASM assembler.
Figure 9-1 shows the general formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Note:
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION
and TRIS instructions.
Byte-oriented le register operations
13
8
7
6
0
d = 0 for destination W
OPCODE
d
f (FILE #)
d = 1 for destination f
f = 7-bit le register address
Bit-oriented le register operations
13
10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit le register address
Literal and control operations
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
13
11
10
0
OPCODE
k (literal)
k = 11-bit immediate value
General
CALL
and GOTO instructions only
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