參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 93/160頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
7-33
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7.4.11.2.1 PattrnMask Register
This register defines which bits in a pixel are blink bits. To enable an individual bit for
comparison requires setting that corresponding bit to “1”. To disable an individual bit for
comparison set the bit position to “0”.
For example, in 8bpp mode, the PattrnMask is defined as 0x0000_0080. This means that the
MSB of a pixel is used to assist is defined as a blink bit.
7.4.11.2.2 BlinkPattrn Register
The “BlinkPattrn” register is used to further refine which pixel pattern defines a blink pixel.
The pixel value is first masked by the PattrnMask value in the “PattrnMask” register and the
result is compared to BlinkPattrn value in the “BlinkPattrn” register. If the comparison results
in a match, the pixel is considered to be a valid blink pixel.
For example:
An 8-bit pixel is defined as 0xAF (0b1010_1111b).
PattrnMask is defined as 0x0000_00C0.
BlinkPattrn is defined as 0x0000_0080.
PattrnMask = 0xC0 defines the two MSBs of 8-bit pixels as potential blink bits. If the two
corresponding MSBs in the BlinkPattrn register are ‘10’ and the two MSBs of the pixel value
are ‘10’, then the pixel of value = 0xAF is a blink pixel. In fact, all pixel values of 10xx_xxxx
are blink pixels. If BlinkPattrn was changed to 0x0000_0048 above, a pixel of value 0xAF
would not be a blink pixel.
7.4.11.2.3 BlinkMask Register
The “BlinkMask” register is only used if the blink mode definition bits M[3:0] in the
“PixelMode” register are set for an AND, OR, or XOR operation. The value in the “BlinkMask”
register is ANDed (clearing bits), ORed (setting bits), or XORed (inverting bits) with a pixel
that addresses the LUT. The mask allows a blinking pixel to jump from a normal color
definition location to a blink color definition location in the LUT.
7.4.11.3 Types of Blinking
Once a pixel has been defined as a blink pixel, it is necessary to provide information on how
that pixel will blink. The blink type provides determines what operations are performed on the
pixel data as it moves through the blink logic to transform it into a blinking pixel.
There are 10 ways to blink a pixel once it has been defined as a blinking pixel. The blink type
is defined by the M[3:0] bits in the “PixelMode” register:
0000 - Blink Disabled
0001 - AND Blinking.
The pixel data is ANDed with the “BlinkMask” register. The modified pixel data will
continue through the pipeline.
LUT Blink:
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