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參數(shù)資料
| 型號(hào)： | AT89C51SND2C-7FTUL |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 67/160頁(yè) |
| 文件大小： | 0K |
| 描述： | IC 8051 MCU FLASH 64K MP3 100BGA |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，IDE/ATAPI，MMC，SPI，UART/USART，USB |
| 外圍設(shè)備： | 音頻，I²S，MP3，PCM，POR，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.3 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TFBGA |
| 包裝： | 托盤 |
| 其它名稱： | AT89C51SND2C7FTUL |
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7-10
DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
words on both the upper and lower half of the bus. The FIFO has an underflow interrupt
indicator that can be used to determine if the system is providing adequate bandwidth and
low enough latency to support the selected display pixel depth, resolution, and refresh rate.
7.4.3 Video Pixel MUX
The pixel reconstruction circuitry uses multiplexers and pipe-line registers to 'unpack' the
video pixels that are output from the video FIFO. The stored FIFO words are transferred 2 at
a time across a 64-bit bus. The multiplexers select a single pixel to go on the 24-bit output
bus based on the P value that is written to the “PixelMode” register. The multiplexers are
controlled by a pixel counter that also increments based on the PixelMode.P value. The
amount and frequency of data read from the FIFO is dependent on the number of bits per
pixel. For example, in 8 bpp configuration (PixelMode.P = 0x2), the 64-bit FIFO output is
changed for every eight pixels. In dual scan mode, selected by writing DSCAN = ‘1’ to the
“PixelMode” register, the upper 32 bits and lower 32 bits are read out in parallel and the
upper-half screen and lower-half screen pixels are unpacked and loaded into the video
stream sequentially.
7.4.4 Blink Function
The Raster Engine provides blinking pixel control circuitry. This circuitry provides a means to
blink pixels at a rate specified by a programmable count of video frames. The number of
video frames for a blink cycle is controlled by the “BlinkRate” register. There is only a single
blink state bit, so all blinking pixels blink at the same programmed frequency. The most
flexible way to blink pixels is to use a look-up-table (LUT). This is done by logically
transforming the address into the look-up-table based on whether the pixel is a blink pixel,
and whether it is currently in the blink state. For example, a red blinking pixel may be set up
to normally address location 0x11 in the look-up-table. When not in the blink state, the color
output from this location would be red. In the blink state, the address could be logically
modified to 0x21. The color stored at the 0x21 location could be green or black or whatever
other color that it is to be used in place of red in the blink state. To define a pixel as blink,
some color information must be sacrificed. For every pixel color, there could be a blinking
version. This would cut the possible number of system colors in half.
For LUT blinking, the address is modified by using a masked AND/OR/XOR function. The
mask is defined in the “BlinkMask” register. Selection of whether the pixel data is ANDed,
ORed, or XORed with the mask is set by writing to the M field in the “PixelMode” register.
The LUT blinking solution is only useful for 4 bpp and 8 bpp modes because the total number
of colors is limited to 256. The extra bit width in 16 bpp and 24 bpp modes is not used.
Therefore, for 16 bpp, and 24 bpp modes, the LUT blink circuitry is usually bypassed (based
on the C field in the “PixelMode” register) and the blink function is performed by logical or
mathematical operations on the pixel data. These operations can be programmed for Blink to
Background, Blink Dimmer, Blink Brighter, or Blink to Offset by writing the appropriate value
to the M field in the “PixelMode” register.
When Blink to Background mode is enabled, the blink circuitry replaces any blinking pixel
with the “BkgrndOffset” register value. Setting this register to the background screen color in
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AT89C51-W | 功能描述:8位微控制器 -MCU Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| AT89C52 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash |
| AT89C52_00 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash |
| AT89C52_99 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash |
| AT89C52-12AA | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash |
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