參數(shù)資料
型號： AT89C51SND2C-7FTUL
廠商： Atmel
文件頁數(shù)： 88/160頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 64K MP3 100BGA
標準包裝： 260
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，IDE/ATAPI，MMC，SPI，UART/USART，USB
外圍設(shè)備： 音頻，I²S，MP3，PCM，POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.3 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TFBGA
包裝： 托盤
其它名稱： AT89C51SND2C7FTUL
7-28
DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7.4.10 Video Timing
The video timing circuitry consists of a horizontal down counter and a vertical down counter.
Signal timing for a specific video format is generated by programmable values that are
compared to the count values.
An AC signal is generated to support either bias voltage switching for LCDs or a field
indicator for interlaced video. The An AC signal, if ACEN = ‘1’ in the “VideoAttribs” register, is
output on the P[17] pin. The toggle rate of the AC signal is selected by writing to the “ACRate”
register.
LCD shifting signals, XECL and YSCL, are generated to support simple LCDs. These signals,
if LCDEN = ‘1’ in the “VideoAttribs” register, are output on pixel data pins P[16] and P[15],
respectively. XECL is generated every 64 pixel clocks. YSCL is the inversion of HSYNCn.
The Raster Engine provides an end of frame interrupt, when enabled, to the interrupt
controller. This interrupt defines when the last information has been sent to the display for the
current frame. It indicates the start of an interval when changes can be made to the LUT or
source for the displayed image without affecting the display. It must be configured as an edge
triggered interrupt. Changes such as a new cursor location or a new screen image location
automatically change at this time, under hardware control. The interval for making LUT
changes, etc. without affecting the displayed image depends on the display’s technology. The
time duration is equal to the vertical blanking interval (VLinesTotal duration - VACTIVE
duration).
In addition, the programmable VCLR and HCLR fields in the “SigClrStr” register are used as
a secondary interrupt during normal operation, where the interrupt can be programmed to
trigger at any vertical and horizontal counter combination.
The frequency of the clock used for video timing and the entire video pipeline must meet the
requirements of the display type. The video clock frequency is selected by writing to the
VidClkDiv register (see Chapter 5). The video circuitry is targeted to run up to 132MHz. This
corresponds to a 1280 pixels by 1024 pixels display size, and non-interlaced video at a 80Hz
frame refresh.
Note: Total Bus/SDRAM bandwidth is shared between the Raster Engine and other device
controllers. The pixel depth, display size, and display refresh rate can be limited by the
Bus/SDRAM bandwidth that is available to the Raster Engine.
The programmed values for the video timing section of the raster engine are shown in
Signals". Independent horizontal and vertical down counters are used as a reference for all
other signals. The synchronization, blanking, and active video control signalling is generated
by comparing programmed values to the counters.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT89C51-W 功能描述:8位微控制器 -MCU Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C52 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
AT89C52_00 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52_99 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52-12AA 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
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