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參數(shù)資料
| 型號(hào)： | AT49BP1604 |
| 廠(chǎng)商： | ATMEL CORP |
| 元件分類(lèi)： | PROM |
| 英文描述： | 16-megabit Burst Mode 3-volt Only Flash Memory(16M位脈沖串模式3V閃速存儲(chǔ)器) |
| 中文描述： | 1M X 16 FLASH 3V PROM, 100 ns, PBGA40 |
| 封裝： | BGA-40 |
| 文件頁(yè)數(shù)： | 2/19頁(yè) |
| 文件大?。?/td> | 263K |
| 代理商： | AT49BP1604 |
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AT49BP1604(T)
2
grammed off a single 2.7V power supply, making it ideally
suited for in-system programming. The output voltage can
be separately controlled down to 1.65V through the VCCQ
supply pin.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors. The end of program or Erase is detected by data
polling, or toggle bit.
A VPP pin is provided to improve program/erase times.
This pin does not need to be utilized. If it is not used the pin
should be connected to ground. To take advantage of
faster programming, the pin should supply 4.5 to 5.5 volts
during program and erase operations.
With V
PP
at 5V, a six byte command to remove the require-
ment of entering the three byte program sequence is
offered to further improve programming time. After entering
the six byte code, only single pulses on the write control
lines are required for writing into the device. This mode is
exited by powering down the device, by taking the RESET
pin to GND
or by a high to low transition on the V
PP
input.
This mode is not exited by the read reset command. Erase,
Erase Suspend/Resume and Read Reset commands will
not work while in this mode; if entered they will result in
data being programmed into the device. It is not recom-
mended that the six byte code reside in the software of the
final product but only exist in external programming code.
Device Operation
RANDOM READ:
The random read operation of the device
is controlled by CE, OE, and AVD inputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention. The data at the address location
defined by AD0-AD15 and A16-A19 and captured by the
AVD signal will be read when CE and OE are low. The
address location passes into the device when CE and AVD
are low; the address is latched on the low to high transition
of AVD. Low input levels on the OE and CE pins allow the
data to be driven out of the device. AVD must be high
whenever OE is low. The access time is measured from
stable address, falling edge of AVD or falling edge of CE,
whichever occurs last. The BAA signal must be held high,
and no clock signal is provided during random reads.
BURST READ:
The burst read operation of the device is
controlled by CE, OE, CLK, BAA and AVD inputs. The initial
read location is determined as for the random read opera-
tion; it can be any memory location in the device. A low
input on the BAA signal indicates that a burst read will
occur. In the burst access, the address is latched on the ris-
ing edge of the first clock pulse when AVD is low or the ris-
ing edge of the AVD signal whichever occurs first. The CLK
signal controls the flow of data from the device for a burst
operation. To perform a burst read, the BAA signal should
go low during the clock cycle prior to the beginning of the
burst. When the BAA signal is low, the data at the next
sequential address in memory is read for each following
clock cycle.
During a given burst mode read, any number of addresses
can be read from the memory. When a page boundary in
the memory is transitioned, additional time may be required
for the device to continue the burst read. To indicate that it
is not ready to continue the burst, the device will drive the
RDY pin low during the clock cycles in which new data is
not being presented. Once the RDY pin is driven high, the
next data will be valid. Starting with address zero, page
boundaries occur every 128 words in the memory. During
the burst mode, depending on the initial address that is
read, the first page boundary transition may occur before
128 words are read. The RDY signal will be tri-stated when
the CE or OE signal is high.
In the “Burst Read Cycle Waveform” as shown on page 13,
the data D0 is valid asynchronously from point A, the point
when the addresses are latched. The low to high transition
of the clock at point B results in no change of data because
the RDY signal is low. The low to high transition of the
clock at point C results in the first burst word, D1, being
read. The transition of the clock at point D results in a burst
read of the last word of the page, D127. The clock transi-
tion at point E does not cause new data to appear on the
output lines because the RDY signal goes low after the
clock transition which signifies that a page boundary in the
memory has been crossed and that new data is not avail-
able. The clock transition at point F does cause a burst
read of data D128 because the RDY signal goes high after
the clock transition indicating that new data is available. As
long as the BAA signal is low, additional clock transitions,
like at point G, will continue to result in burst reads until the
next page boundary is crossed between word D255 and
D256.
COMMAND SEQUENCES:
The device powers on in the
read mode. Command sequences are used to place the
device in other operating modes such as program and
erase. The command sequences are written by applying a
low pulse on the WE input with CE low and OE high. Prior
to the low going pulse on the WE signal, the address input
must be latched by a low to high transition on the AVD sig-
nal. Valid data is asserted when the WE signal is low and
latched on the rising edge of the WE pulse. The addresses
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