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參數(shù)資料
| 型號： | AT45BR3214B |
| 廠商： | Atmel Corp. |
| 英文描述： | 32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY |
| 中文描述： | 32-MEGABIT的DataFlash 4兆位的SRAM堆棧內(nèi)存 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 488K |
| 代理商： | AT45BR3214B |
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AT45BR3214B
3356B–DFLASH–10/04
cycle, allowing one continuous read operation without the need of additional address
sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked
into the device followed by 24 address bits and 32 don’t care bits. The first bit of the
24-bit address sequence is reserved for upward and downward compatibility to larger
and smaller density devices (see Notes under “Command Sequence for Read/Write
Operations” diagram). The next 13 address bits (PA12 - PA0) specify which page of the
main memory array to read, and the last ten bits (BA9 - BA0) of the 24-bit address
sequence specify the starting byte address within the page. The 32 don’t care bits that
follow the 24 address bits are needed to initialize the read operation. Following the 32
don’t care bits, additional clock pulses on the SCK pin will result in serial data being out-
put on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t
care bits, and the reading of data. When the end of a page in main memory is reached
during a Continuous Array Read, the device will continue reading at the beginning of the
next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the
main memory array has been read, the device will continue reading back at the begin-
ning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the
array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the
SO pin. The maximum SCK frequency allowable for the Continuous Array Read is
defined by the f
CAR
specification. The Continuous Array Read bypasses both data buff-
ers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ:
A Main Memory Page Read allows the user to read data
directly from any one of the 8192 pages in the main memory, bypassing both of the data
buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of 52H or D2H must be clocked into the device followed by 24 address bits and
32 don’t care bits. The first bit of the 24-bit address sequence is a reserved bit, the next
13 address bits (PA12 - PA0) specify the page address, and the next ten address bits
(BA9 - BA0) specify the starting byte address within the page. The 32 don’t care bits
which follow the 24 address bits are sent to initialize the read operation. Following the
32 don’t care bits, additional pulses on SCK result in serial data being output on the SO
(serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data. When the end of a page in
main memory is reached during a Main Memory Page Read, the device will continue
reading at the beginning of the same page. A low-to-high transition on the CS pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ:
Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read
data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To
perform a Buffer Read, the eight bits of the opcode must be followed by 14 don’t care
bits, ten address bits, and eight don’t care bits. Since the buffer size is 528 bytes, ten
address bits (BFA9 - BFA0) are required to specify the first byte of data to be read from
the buffer. The CS pin must remain low during the loading of the opcode, the address
bits, the don’t care bits, and the reading of data. When the end of a buffer is reached,
the device will continue reading back at the beginning of the buffer. A low-to-high transi-
tion on the CS pin will terminate the read operation and tri-state the SO pin.
STATUS REGISTER READ:
The status register can be used to determine the device’s
Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or
the device density. To read the status register, an opcode of 57H or D7H must be
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT45BR3214B-C1 | 32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY |
| AT45CS1282 | 128-megabit 2.7-volt Dual-interface Code Shadow DataFlash |
| AT45D011 | 1-Megabit 5.0-volt Only Serial DataFlash |
| AT45D011-JC | 1-Megabit 5.0-volt Only Serial DataFlash |
| AT45D011-JI | 1-Megabit 5.0-volt Only Serial DataFlash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT45BR3214B-C1 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY |
| AT45CS1282 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:128-megabit 2.7-volt Dual-interface Code Shadow DataFlash |
| AT45CS1282-TC | 功能描述:閃存 128M bit RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AT45CS1282-TI | 功能描述:IC FLASH 128MBIT 50MHZ 40TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| AT45D011 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1-Megabit 5.0-volt Only Serial DataFlash |
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