參數(shù)資料
型號(hào): AT45BR3214B
廠商: Atmel Corp.
英文描述: 32-MEGABIT DATAFLASH + 4-MEGABIT SRAM STACK MEMORY
中文描述: 32-MEGABIT的DataFlash 4兆位的SRAM堆棧內(nèi)存
文件頁(yè)數(shù): 5/40頁(yè)
文件大小: 488K
代理商: AT45BR3214B
5
AT45BR3214B
3356B–DFLASH–10/04
Memory Architecture Diagram
Device Operation
The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode
and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main
memory address location through the SI (serial input) pin. All instructions, addresses
and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to
denote the ten address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA12 - PA0 and BA9 - BA0
where PA12 - PA0 denotes the 13 address bits required to designate a page address
and BA9 - BA0 denotes the ten address bits required to designate a byte address within
the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 11 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.
CONTINUOUS ARRAY READ:
By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
SECTOR 0 = 4224 bytes (4K + 128)
SECTOR 1 = 266,112 bytes (252K + 8064)
SECTOR 15 = 270,336 bytes (256K + 8K)
Block = 4224 bytes
(4K + 128)
8 Pages
SECTOR 0
S
Page = 528 bytes
(512 + 16)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 8190
PAGE 8191
B
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 8189
B
SECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 1022
BLOCK 1023
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
S
SECTOR 2 = 270,336 bytes (256K + 8K)
SECTOR 16 = 270,336 bytes (256K + 8K)
BLOCK 2
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參數(shù)描述
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AT45CS1282-TC 功能描述:閃存 128M bit RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
AT45CS1282-TI 功能描述:IC FLASH 128MBIT 50MHZ 40TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M(2M x 8,1M x 16) 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP(0.724",18.40mm 寬) 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤
AT45D011 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1-Megabit 5.0-volt Only Serial DataFlash