參數(shù)資料
型號: AT17LV256A
廠商: Atmel Corp.
英文描述: 256K FPGA Configuration EEPROM Memory(256K 現(xiàn)場可編程門陣列(FPGA)配置EEPROM存儲器)
中文描述: 256K FPGA配置存儲器(256K現(xiàn)場可編程門陣列(FPGA)的配置的EEPROM存儲器)
文件頁數(shù): 9/14頁
文件大小: 227K
代理商: AT17LV256A
AT17C/LV65A/128A/256A
9
Notes:
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady-state active levels.
AC Characteristics for AT17C65A/128A
V
CC
= 5V ± 5% Commercial / V
CC
= 5V ± 10% Ind./Mil.
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
OE
(2)
OE to Data Delay
30
35
ns
T
CE
(2)
nCS to Data Delay
50
50
ns
T
CAC
(2)
DCLK to Data Delay
50
55
ns
T
OH
Data Hold From nCS, OE, or DCLK
0
0
ns
T
DF
(3)
nCS or OE to Data Float Delay
50
50
ns
T
LC
DCLK Low Time
30
35
ns
T
HC
DCLK High Time
30
35
ns
T
SCE
nCS Setup Time to DCLK (to guarantee proper counting)
45
50
ns
T
HCE
nCS Hold Time from DCLK (to guarantee proper counting)
0
0
ns
T
HOE
OE Low Time (guarantees counter is reset)
25
25
ns
F
MAX
MAX Input Clock Frequency
12.5
12.5
MHz
AC Characteristics for AT17C128A When Cascading
V
CC
= 5V ± 5% Commercial / V
CC
= 5V ± 10% Ind./Mil.
Symbol
Description
Commercial
Industrial/Military
(1)
Units
Min
Max
Min
Max
T
CDF
(3)
DCLK to Data Float Delay
50
50
ns
T
OCK
(2)
DCLK to nCASC Delay
55
60
ns
T
OCE
(2)
nCS to nCASC Delay
55
60
ns
T
OE
(2)
OE to nCASC Delay
40
45
ns
F
MAX
MAX Input Clock Frequency
8
8
MHz
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