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參數(shù)資料
| 型號： | AT17LV256A |
| 廠商： | Atmel Corp. |
| 英文描述： | 256K FPGA Configuration EEPROM Memory(256K 現(xiàn)場可編程門陣列（FPGA）配置EEPROM存儲器) |
| 中文描述： | 256K FPGA配置存儲器（256K現(xiàn)場可編程門陣列（FPGA）的配置的EEPROM存儲器） |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 227K |
| 代理商： | AT17LV256A |
AT17C/LV65A/128A/256A
5
Note:
1. To order the 8-lead PDIP version refer to
“
FPGA Configuration EEPROM Memory: 64K, 128K and 256K
”
(doc.# 0391).
Pin Configurations
8 DIP
(1)
20 PLCC
Pin
2
Pin
1
Name
DATA
I/O
I/O
Description
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic
level resets the address counter. A High logic level (with nCS Low) enables DATA and
permits the address counter to count. The logic polarity of OE is programmable and must
be set active High (RESET active Low) by the user during programming for Altera
applications.
Write Protect (WP) input (when nCS is Low) during programming only (i.e., when
SER_EN is Low). When WP is Low, the entire memory can be written. When WP is
enabled (High), the lowest block of the memory cannot be written. This function is not
available during FPGA loading operations. Please refer to the
“
Programming
Specification
”
application note for more details.
Chip select input (active Low). A Low input (with OE active) allows DCLK to increment
the address counter and enables DATA to drive out. A High level on nCS disables both
the address and bit counters and forces the device into a low-power standby mode. Note
that this pin will not enable/disable the device in the 2-wire Serial Programming Mode
(i.e., when SER_EN is Low).
Ground pin. A 0.2 μF decoupling capacitor should be placed between the VCC and
GND pins.
Cascade select output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of
one device must be connected to the nCS input pin of the next device in the chain. It will
stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE goes
Low, thereafter, nCASC will stay High until the entire EEPROM is read again.
Device selection input, A2. This is used to enable (or select) the device during
programming (i.e., when SER_EN is Low; please refer to the
“
Programming
Specification
”
application note for more details).
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode.
+3.3V/+5V Power Supply Pin.
4
2
DCLK
I
8
3
OE
I
WP
I
9
4
nCS
I
10
5
GND
12
6
nCASC
O
A2
I
18
7
SER_EN
I
20
8
VCC
Absolute Maximum Ratings*
Operating Temperature..................................-55
°
C to +125
°
C
*NOTICE:
Stresses beyond those listed under
“
Absolute
Maximum Ratings
”
may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature.....................................-65
°
C to +150
°
C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to V
CC
+0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260
°
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)................................. 2000V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT17LV256A-10BJC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10BJI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10CC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10CI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:FPGA Configuration EEPROM Memory |
| AT17LV256A-10JC | 功能描述:IC SRL CONFG EEPROM 256K 20-PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
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